Engineering topics
Publications and source records attributed to Wade, T. E..
Four-volume document reviews key technologies for interconnecting in very-large-scale integrated (VLSI) circuits. Document also discusses current and proposed research into novel fabrication techniques for interconnections.
A multilevel metal interconnection system for very large scale integration (VLSI) systems utilizing polyimides as the interlayer dielectric material is described. A complete characterization of polyimide materials is given as well as experimental methods accomplished using a double level metal test pattern. A low temperature, double exposure polyimide patterning procedure is also presented.
Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.
An accurate study and evaluation of dielectric thin films is conducted in order to find the material or combination of materials which would optimize NASA'S double layer metal process. Emphasis is placed on polyimide dielectrics because of their reported outstanding dielectric characteristics (including electrical, chemical, thermal, and mechanical) and ease of processing, as well as their rapid acceptance by the semiconductor industry.
The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.
Postsintering process increases yield of double-layer metal conductors to almost 100 percent. When wafers containing double-metalized chips are sintered, metal layers react with oxide film remaining in insulation layer holes, breaking it up so that it no longer impedes electric current. Cooling also mechanically disrupts oxide film.
Report describes one-year research effort in VLSL fabrication. Four activities are described: theoretical study of two-dimensional diffusion in SOS (silicon-on-sapphire); setup of sputtering system, furnaces, and photolithography equipment; experiments on double layer metal; and investigation of two-dimensional modeling of MOSFET's (metal-oxide-semiconductor field-effect transistors).
Acquisition of polyimide materials for inter-metal dielectrics was obtained from three vendors, with considerable evaluation conducted on the Dupont PI2550 material. Experimental results indicate this material can be patterned using contact printing to line width far below 0.1 mils. Optimum line width is acquired using plasma etch equipment. Metal lift-off experiments on thermal evaporated films were optimized for application to sputtered deposited films. Alternate metal-lift-off experiments are proposed for future investigation. Dry processing equipment studies and future trends in VLSI fabrication techniques are on-going.
Polyimide dielectric materials were acquired for comparative and evaluative studies in double layer metal processes. Preliminary experiments were performed. Also, the literature indicates that sputtered aluminum films may be successfully patterned using the left-off technique provided the substrate temperature remains low and the argon pressure in the chamber is relatively high at the time of sputtering. Vendors associated with dry processing equipment are identified. A literature search relative to future trends in VLSI fabrication techniques is described.
Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.
The research facilities of the Mississippi State University devoted to microelectronics are described. The fabrication and processing capabilities, computer aided design, and experimental evaluation capabilities are discussed.
The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized.
The realization of high yield double layer metal systems using wet chemistry processes and the ability to extend yields beyond that attainable with wet chemistry by means of post sintering processes at temperatures below 500 C for potential applications in very large scale integration structures were studied. Yields in excess of 98% and average total contact resistance of less than 150 ohms and 200 ohms were realized for a series of 560 vias of 0.5 X 0.5 mils and 0.2 X 0.2 mils in size, respectively.
Furnaces and photolithography related equipment were applied to experiments on double layer metal. The double layer metal activity emphasized wet chemistry techniques. By incorporating the following techniques: (1) ultrasonic etching of the vias; (2) premetal clean using a modified buffered hydrogen fluoride; (3) phosphorus doped vapor; and (4) extended sintering, yields of 98 percent were obtained using the standard test pattern. The two dimensional modeling problems have stemmed from, alternately, instability and too much computation time to achieve convergence.
A sputtering system was developed to deposit aluminum and aluminum alloys by the dc sputtering technique. This system is designed for a high level of cleanliness and for monitoring the deposition parameters during film preparation. This system is now ready for studying the deposition and annealing parameters upon double-level metal preparation. A technique recently applied for semiconductor analysis, the finite element method, was studied for use in the computer modeling of two dimensional MOS transistor structures. It was concluded that the method has not been sufficiently well developed for confident use at this time. An algorithm was developed for confident use at this time. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program which was developed was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients.