Analysis of limit cycles in a two-transistor saturable-core parallel inverter.
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.
It recently has been shown in the literature that many dc-to-square-wave parallel inverters which are widely used in power-conditioning applications can be grouped into one of two families. Each family is characterized by an equivalent RLC network. Based on this approach, a classification procedure is presented for self-oscillating parallel inverters which makes evident natural relationships which exist between various inverter configurations. By utilizing concepts from the basic theory of negative resistance oscillators and the principle of duality as applied to nonlinear networks, a chain of relationships is established which enables a methodical transfer of knowledge gained about one family of inverters to any of the other families in the classification array.
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A statistical summary of electrical characterization was performed on JANTX 1N5619 silicon diodes. Parameters are presented with test conditions, mean, standard deviation, lowest reading, 10% point, 90% point, and highest reading.
The data processing and calculation of statistical parameters was performed by the Tektronix computer system. The data acquired for easy vendor to vendor and date code to date code analysis are summarized. Each parameter is presented with test conditions, mean, standard deviation, lowest reading, 10% point (where 10% of all readings are equal to or less than the indicated reading), 90% point (where 90% of all readings are equal to or less than the indicated reading) and the highest reading.
The necessary data to create a new class of specifications was the objective of this characterization program. Sample selection was made according to the following criteria: (1) manufacturer or qualified distributor; (2) two vendors; and (3) two date codes. The general guidelines for procurement were two QPL vendors, JAN or JANTX, and two manufacturing lots, 27 from each lot. All data were acquired with three digit accuracy. The data processing and calculation of statistical parameters were performed by the Tektronix computer system using 4 digit display.
The effect of power and temperature stresses when applied to a variety of semiconductor devices is summarized.
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The paper presents an analytical treatment of transparent-emitter devices, particularly solar cells, that is more complete than previously available treatments. The proposed approach includes the effects of bandgap narrowing, Fermi-Dirac statistics, built-in field due to impurity profile, and a finite surface recombination velocity at the emitter surface. It is demonstrated that the transparent-emitter model can predict experimental values of Voc observed on n(plus)-p thin diffused junction silicon solar cells made on low-resistivity (0.1 ohm-cm) substrates. A test is included for the self-consistent validity of the transparent-emitter model. This test compares the calculated transit time of minority carriers across the emitter with the Auger-impact minority-carrier lifetime within the emitter region.
Report describes effects of power and temperature overstress on Motorola and Raytheon devices. Motorola devices were weak in power overstress. Raytheon devices succumbed to 160 hour temperature stress. Failure modes are detailed.
Report describes effects of power and temperature overstress on Texas Instruments and National Semiconductor devices. Texas Instruments devices had only two failures in 2500 hours of testing. National Semiconductor devices reached 50% failure limit. No consistent failure mode was detected.
Report evaluates effects of power and temperature overstress on Crystalonics and Texas Instruments devices. Crystalonics devices survived better, as Texas Instruments lot exceeded 50 percent failure at 225 deg C. Failure modes are evaluated.
Report evaluates effects of power and temperature overstress on Raytheon and Teledyne devices. Power overstress produced few failures. Both lots of devices exceeded 50 percent failure at 250 deg C. Failure modes are evaluated.
Report evaluates effects of power and temperature overstress on Raytheon and National Semiconductor devices. Breakdown voltage hysteresis, possibly due to contamination of semiconductor by gold from leads, was prominent.
Report evaluates effects of power and temperature overstress on Motorola and Texas Instruments devices. A variety of failure modes are described.