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The effect is reported of power/temperature step stress when applied to the transistor JANTX2N2369A manufactured by Raytheon and National Semiconductor. A total of 48 samples from each manufacturer was submitted to the process. In addition, two control sample units were maintained for verification of the electrical parametric testing. The power/thermal stress tests are described, and failure analyses are presented.
Data compiled for the purpose of evaluating the effect of power/temperature step stress when applied to the transistor JANTX2N2945A manufactured by Raytheon and Teledyne is presented. A total of 48 samples from each manufacturer was divided equally (16 per group) into three groups and submitted to the processes outlined. In addition, two control units were maintained for verification of the electrical parametric testing.
The effect of power/temperature step stress when applied to the transistor JANTX2N2484, manufactured by Raytheon and Teledyne was evaluated. Forty-eight samples from each manufacturer were divided equally (16 per group) into three groups and submitted to the processes outlined. In addition, two control sample units were maintained for verification of the electrical parametric testing.
A manufacturer was contracted to screen 125 transistors capable of withstanding the high level inductive voltages obtained when switching inductive loads. Planned differences included a change in die bonding to comply with NASA's desire for hard solder die attachment which further necessitated a change in package to conform to the required die mounting system. Evaluation of the electrical performance and recommended changes were made during the preliminary build phase of the program. The following sections are outlined: (1) narrative outline; (2) customer data summary and X-ray reports; (3) device specification; (4) failure analysis reports; (5) test facilities list; and (6) test measurement data.
A model for bipolar junction power switching transistors whose parameters can be readily obtained by the circuit design engineer, and which can be conveniently incorporated into standard computer-based circuit analysis programs is presented. This formulation results from measurements which may be made with standard laboratory equipment. Measurement procedures, as well as a comparison between actual and computed results, are presented.
A rigorous analytic evaluation of an emitter model that includes Auger recombination but excludes bandgap narrowing is presented. It is shown that such a model cannot explain the experimentally observed values of the open-circuit voltage in p-n-junction silicon solar cells. Thus physical mechanisms in addition to Auger recombination are responsible for the experimentally observed values of the open-circuit voltage in silicon solar cells and the common-emitter current gain in bipolar transistors.
Report describes effects of power and temperature overstress on National Semiconductor and Raytheon transistors. Good junction quality was maintained. Gain losses predominated. Other failures are reported.
The ionizing radiation effects of electrons on bipolar transistors have been analyzed using the data base from the Voyager project. The data were subjected to statistical analysis, leading to a quantitative characterization of the product and to data on confidence limits which will be useful for circuit design purposes. These newly-developed methods may form the basis for a radiation hardness assurance system. In addition, an attempt was made to identify the causes of the large variations in the sensitivity observed on different product lines. This included a limited construction analysis and a determination of significant design and processes variables, as well as suggested remedies for improving the tolerance of the devices to radiation.
The proposed dc model for bipolar junction power switching transistors is based on measurements which may be made with standard laboratory equipment. Those nonlinearities which are of importance to power electronics design are emphasized. Measurements procedures are discussed in detail. A model formulation adapted for use with a computer program is presented, and a comparison between actual and computer-generated results is made.
A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.
The design, wafer-processing techniques, and various measurements which include forward safe operating area, dc characteristics, and switching times are described for a larger-diameter (33) transistor. An improved base contact for equalizing the base-emitter voltage at high currents was developed along with an improved emitter contact preform which increases the silicon area available for current conduction. The electrical performance achieved is consistent with the proposed optimum design.
The switching properties of power transistors are investigated. The devices studied were housed in IO-3 cases and were of an n(+)-p-n(-)-n(+) vertical dopant structure. The effects of the magnitude of the reverse-base current and temperature on the reverse-bias second breakdown characteristics are discussed. Brief discussions of device degradation due to second breakdown and of a constant voltage turn-off circuit are included. A description of a vacuum tube voltage clamp circuit which reduces clamped collector voltage overshoot is given.
The cell placement techniques developed for use with the standard transistor array were incorporated in the cell arrangement program for STAR (CAPSTAR). Instructions for use of this program are given.
Instructions are given for updating and maintaining the cell arrangement program for the standard transistor array (CAPSTAR).
A one-dimensional theoretical model of the tandem junction solar cell (TJC) with base resistivity greater than about 1 ohm-cm and under low level injection has been derived. This model extends a previously published conceptual model which treats the TJC as an npn transistor. The model gives theoretical expressions for each of the Ebers-Moll type currents of the illuminated TJC and allows for the calculation of the spectral response, I(sc), V(oc), FF and eta under variation of one or more of the geometrical and material parameters and 1MeV electron fluence. Results of computer calculations based on this model are presented and discussed. These results indicate that for space applications, both a high beginning of life efficiency, greater than 15% AM0, and a high radiation tolerance can be achieved only with thin (less than 50 microns) TJC's with high base resistivity (greater than 10 ohm-cm).
Standard Transistor Array (STAR) design system is semicustom approach to generating random-logic integrated MOS digital circuits. Primary program in STAR system is CAPSTAR, STAR Cell Arrangement Program. CAPSTAR is augmented by automatic routining program, Display program and library of logic cells.
Dc to dc converters which operate reliably and efficiently at switching frequencies high enough to effect substantial reductions in the size and weight of converter energy storage elements are studied. A two winding current or voltage stepup (buck boost) dc-to-dc converter power stage submodule designed to operate in the 2.5-kW range, with an input voltage range of 110 to 180 V dc, and an output voltage of 250 V dc is emphasized. In order to assess the limitations of present day component and circuit technologies, a design goal switching frequency of 10 kHz was maintained. The converter design requirements represent a unique combination of high frequency, high voltage, and high power operation. The turn off dynamics of the primary circuit power switching transistor and its associated turn off snubber circuitry are investigated.
Component holder speeds examination of matched pairs. Transistors are oriented for two perpendicular x-ray views. Second view obtained by simply flipping block around corner near components, while corner remains in contact with film. Procedure allows inspection of up to 50 pairs - two views of each pair - on single x-ray film in same time previously required for 1 unmounted pair.