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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2021

Development of Gallium Nitride Monolithic Microwave Integrated Circuits for Ka-Band Remote Sensing

We have been developing gallium nitride (GaN)monolithic microwave integrated circuits (MMICs) towards thegoal of implementing a single chip transceiver frontend forcloud radar arrays at Ka-band. We present our first iterationdesign, fabrication and test cycle implementation of GaN poweramplifiers (PAs), low noise amplifiers (LNAs), driver amplifier,single-pole- double and triple throw switches, and voltagecontrolled attenuator. These components are necessary forimplementing a transceiver unit cell concept with digitalcalibration capabilities to enable scalable array sizes for radarand radiometry.

Cao, Yu↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS1980

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.↗
NASA NTRS1991

Post irradiation effects (PIE) in integrated circuits

Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

Shaw, D. C.↗
NASA NTRS2005

Integrated circuit cell library

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Whitaker, Sterling R.↗
NASA NTRS2019

Integrated Circuit (IC) Chip with a Self-Contained Fluid Sensor and Method of Making the Chip

An integrated circuit (IC) chip with a self-contained fluid sensor and method of making the chip. The sensor is in a conduit formed between a semiconductor substrate and a non-conductive cap with fluid entry and exit points through the cap. The conduit may be entirely in the cap, in the substrate or in both. The conduit includes encased temperature sensors at both ends and a central encased heater. The temperature sensors may each include multiple encased diodes and the heater may include multiple encased resistors.

Manos, George↗
NASA NTRS2019

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

While NASA Glenn Research Center's "Generation 10" 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100- and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Spry, D. J.↗
NASA NTRS1968

Dc pin-to-pin testing of integrated circuits

External pin-to-pin nondestructive testing procedure measures the electrical characteristics of each element in an integrated circuit. The procedure involves choosing specific pairs of pins and applying appropriate test voltages to them.

Thomas, E. F.↗
NASA NTRS1977

Optical integrated-circuit tester

Computer controlled device can check typical medium scale unit in less than one minute. System scans integrated circuit chip with narrow beam of light while simultaneously scanning reference chip.

Micka, E. A.↗
NASA NTRS1985

Designing Test Chips for Custom Integrated Circuits

Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

Buehler, M. G.↗
NASA NTRS2023

An Examination of Heavy Ion-Induced Persistent Visual Error Signatures in an Electronic Display Driver Integrated Circuit

Given the ubiquity of electronic displays integration in human-based systems, the impending mission critical, space-based applications of electronic displays will necessitate SEE assessment of components unique to electronic displays. A commercially available DDIC designed to drive a small form factor organic light emitting diode (OLED) was visually monitored during heavy ion irradiation to catalogue radiation induced persistent visual error signatures that require manual intervention (i.e., power cycling) to return to nominal function. These error signatures were able to be reproduced via modification of configuration register values utilizing the instruction set intended for interfacing a microcontroller with the DDIC. This approach to emulation of heavy-ion induced errors on a table-top assists with human perception-based criticality analysis as well as development of mitigation techniques.

Electronic Displays↗
NASA NTRS1967

Method of improving contact bonds in silicon integrated circuits

Fabrication method produces stable and reliable metallic systems for interconnections, contact pads, and bonded leads in silicon planar integrated circuits. The method is based on substrate isolation of the interconnection metal from the contact pad and bonded wire.

Lytle, W. J.↗
NASA NTRS1969

Improved method of dicing integrated circuit wafers into chips

Method employing a pressure chamber is used for dicing semiconductor single-crystal wafers, containing integrated circuits, into small chips along pre-scribed lines. Uniform bending of the scribed wafer over the convex surface of a perforated hemisphere, breaks it cleanly into individual chips without damaging the circuits.

Litant, I.↗