NASA NTRS · 19850000032
Designing Test Chips for Custom Integrated Circuits
Abstract
Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.
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Buehler, M. G., Griswold, T. W., Pina, C. A., Timoc, C. C.. 1985-06-01. Designing Test Chips for Custom Integrated Circuits. https://ntrs.nasa.gov/citations/19850000032
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