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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Flash memory reliability NEPP 2008 task final report

This is the preliminary report which is based on the flash memory reliability studies conducted during the first year (2008) of the multi-year NEPP task. The report outlines the technology and reliability challenges for advanced flash memory technologies, summarizes the test results and analyses of reliability characterizations performed on the selected flash memory devices during 2008, and provides the preliminary thoughts on the risk mitigation approaches on using advanced flash memory technologies for space applications.

Chen, Yuan↗
NASA NTRS2010

Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

latency↗
NASA NTRS2002

Very Large Scale Optimization

The purpose of this research under the NASA Small Business Innovative Research program was to develop algorithms and associated software to solve very large nonlinear, constrained optimization tasks. Key issues included efficiency, reliability, memory, and gradient calculation requirements. This report describes the general optimization problem, ten candidate methods, and detailed evaluations of four candidates. The algorithm chosen for final development is a modern recreation of a 1960s external penalty function method that uses very limited computer memory and computational time. Although of lower efficiency, the new method can solve problems orders of magnitude larger than current methods. The resulting BIGDOT software has been demonstrated on problems with 50,000 variables and about 50,000 active constraints. For unconstrained optimization, it has solved a problem in excess of 135,000 variables. The method includes a technique for solving discrete variable problems that finds a "good" design, although a theoretical optimum cannot be guaranteed. It is very scalable in that the number of function and gradient evaluations does not change significantly with increased problem size. Test cases are provided to demonstrate the efficiency and reliability of the methods and software.

Vanderplaats, Garrett↗
NASA NTRS1982

Bubble domain technology for spacecraft onboard memory

Bubble device technologies for spacecraft onboard memory offer improved reliability and memory functional characteristics. Recent advances include Permalloy gap devices (commercially available) whose improved performance and higher density are attributable to an asymmetric chevron pattern. Secondly, an order of magnitude increase in density at less power than the Permalloy technology is possible with the ion implant technology. A third technology, the self-structured current access system, offers another order of magnitude improvement in density and data rate, and is being studied. Capacity estimates for Permalloy gap, ion implant, and self-structured current access systems are, respectively, 10 to the 8th, 10 to the 9th, and 10 to the 10th bits, and power per unit data rate efficiencies are 140, 60, and 2 W/Mbps. A flexible modular organization system, compatible with all of these device technologies, is analyzed, and, as the system is contained in a bubble, relatively simple retrofitting is foreseen.

Hayes, P. J.↗
NASA NTRS1973

Modeling of a bubble-memory organization with self-checking translators to achieve high reliability.

Study of the design and modeling of a highly reliable bubble-memory system that has the capabilities of: (1) correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and (2) detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The results of the study justify the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability.

Bouricius, W. G.↗
NASA NTRS1994

Improved Reading Gate For Vertical-Bloch-Line Memory

Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

Wu, Jiin-Chuan↗
NASA NTRS2002

Advanced Engine Cycles Analyzed for Turbofans With Variable-Area Fan Nozzles Actuated by a Shape Memory Alloy

Advanced, large commercial turbofan engines using low-fan-pressure-ratio, very high bypass ratio thermodynamic cycles can offer significant fuel savings over engines currently in operation. Several technological challenges must be addressed, however, before these engines can be designed. To name a few, the high-diameter fans associated with these engines pose a significant packaging and aircraft installation challenge, and a large, heavy gearbox is often necessary to address the differences in ideal operating speeds between the fan and the low-pressure turbine. Also, the large nacelles contribute aerodynamic drag penalties and require long, heavy landing gear when mounted on conventional, low wing aircraft. Nevertheless, the reduced fuel consumption rates of these engines are a compelling economic incentive, and fans designed with low pressure ratios and low tip speeds offer attractive noise-reduction benefits. Another complication associated with low-pressure-ratio fans is their need for variable flow-path geometry. As the design fan pressure ratio is reduced below about 1.4, an operational disparity is set up in the fan between high and low flight speeds. In other words, between takeoff and cruise there is too large a swing in several key fan parameters-- such as speed, flow, and pressure--for a fan to accommodate. One solution to this problem is to make use of a variable-area fan nozzle (VAFN). However, conventional, hydraulically actuated variable nozzles have weight, cost, maintenance, and reliability issues that discourage their use with low-fan-pressure-ratio engine cycles. United Technologies Research, in cooperation with NASA, is developing a revolutionary, lightweight, and reliable shape memory alloy actuator system that can change the on-demand nozzle exit area by up to 20 percent. This "smart material" actuation technology, being studied under NASA's Ultra-Efficient Engine Technology (UEET) Program and Revolutionary Concepts in Aeronautics (RevCon) Program, has the potential to enable the next generation of efficient, quiet, very high bypass ratio turbofans. NASA Glenn Research Center's Propulsion Systems Analysis Office, along with NASA Langley Research Center's Systems Analysis Branch, conducted an independent analytical assessment of this new technology to provide strategic guidance to UEET and RevCon. A 2010-technology-level high-spool engine core was designed for this evaluation. Two families of low-spool components, one with and one without VAFN's, were designed to operate with the core. This "constant core" approach was used to hold most design parameters constant so that any performance differences between the VAFN and fixed nozzle cycles could be attributed to the VAFN technology alone. In this manner, the cycle design regimes that offer a performance payoff when VAFN's are used could be identified. The NASA analytical model of a performance-optimized VAFN turbofan with a fan pressure ratio of 1.28 is shown. Mission analyses of the engines were conducted using the notional, long-haul, advanced commercial twinjet shown. A high wing design was used to accommodate the large high-bypassratio engines. The mission fuel reduction benefit of very high bypass shape-memory-alloy VAFN aircraft was calculated to be 8.3 percent lower than a moderate bypass cycle using a conventional fixed nozzle. Shape-memory-alloy VAFN technology is currently under development in NASA's UEET and RevCon Programs.

Berton, Jeffrey J.↗
NASA NTRS1991

Architecture for Survivable System Processing (ASSP)

The Architecture for Survivable System Processing (ASSP) Program is a multi-phase effort to implement Department of Defense (DOD) and commercially developed high-tech hardware, software, and architectures for reliable space avionics and ground based systems. System configuration options provide processing capabilities to address Time Dependent Processing (TDP), Object Dependent Processing (ODP), and Mission Dependent Processing (MDP) requirements through Open System Architecture (OSA) alternatives that allow for the enhancement, incorporation, and capitalization of a broad range of development assets. High technology developments in hardware, software, and networking models, address technology challenges of long processor life times, fault tolerance, reliability, throughput, memories, radiation hardening, size, weight, power (SWAP) and security. Hardware and software design, development, and implementation focus on the interconnectivity/interoperability of an open system architecture and is being developed to apply new technology into practical OSA components. To insure for widely acceptable architecture capable of interfacing with various commercial and military components, this program provides for regular interactions with standardization working groups (e.g.) the International Standards Organization (ISO), American National Standards Institute (ANSI), Society of Automotive Engineers (SAE), and Institute of Electrical and Electronic Engineers (IEEE). Selection of a viable open architecture is based on the widely accepted standards that implement the ISO/OSI Reference Model.

Wood, Richard J.↗
NASA NTRS2012

NAND Flash Qualification Guideline

Better performing Forward Error Correction on the forward link along with adequate power in the data open an uplink operations trade space that enable missions to: Command to greater distances in deep space (increased uplink margin). Increase the size of the payload data (latency may be a factor). Provides space for the security header/trailer of the CCSDS Space Data Link Security Protocol. Note: These higher rates could be used for relief of emergency communication margins/rates and not limited to improving top-end rate performance. A higher performance uplink could also reduce the requirements on flight emergency antenna size and/or the performance required from ground stations. Use of a selective repeat ARQ protocol may increase the uplink design requirements but the resultant development is deemed acceptable, due the factor of 4 to 8 potential increase in uplink data rate.

Floating Gate Memory↗
NASA NTRS2010

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗