Hardware Design of a 13.8-kV/3-MVA PV Plus Storage Solid-State Transformer (PVS-SST)
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This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.
This paper presents a design of a 10 kV silicon carbide (SiC) MOSFET based modular multilevel converter (MMC). The MMC functions as the interconnection between a 24 kV dc bus and a 13. SkV distribution grid. This paper focuses on the hardware design of the MMC and its submodules. The gate driver, auxiliary power supply and bus bur in submodules are major components that need to meet high dv/dt immunity and high insulation voltage requirements. The gate driver achieves over 200 kV/us common mode transient immunity (CMTI). Its associated auxiliary power supply is based on an on-board transformer with over 30 kV insulation capability and 1.4 pF barrier capacitance. The busbar achieves less than 11 kV/cm electric field in the air to avoid partial discharges. Validation tests of the MMC submodule were performed by double pulse tests at 5 kV and buck converter tests at3 kV, 52A (peak). Reliable operations were achieved in validation tests.
The ongoing work involves 1) the identification and evaluation of various electric signals as indicators to module failure and precursors to aging, and 2) the development of corresponding detection techniques. In the current phase, 1) the increase of on-state resistance is selected as the precursor to the power cycle aging of silicon carbide power MOSFET modules based on review and rest data. 2) A detection method leveraging the gate voltage fluctuations magnitude during commutation transients to inform the on-state resistance increase is investigated which has the benefit of being able to be integrated into the gate driver. A dedicated detection circuit for implementation is designed and simulated and is currently in fabrication.
This paper describes modeling and experimental work to design and demonstrate a silicon carbide (SiC), single-side-cooled power module. Two SiC metal-oxide-semiconductor field-effect transistors (MOSFET) were used for each switch position and packaged on a metalized ceramic substrate. Thermal modeling was first conducted to optimize the module packaging to minimize junction-to-fluid thermal resistance and device temperature variations. This procedure identified the optimal device placement and baseplate thickness to maximize thermal performance. A heat exchanger - incorporating impinging jets of water-ethylene glycol - was designed to cool the module's baseplate to minimize thermal resistance and pumping power. The heat exchanger used relatively low fluid velocities (<1.5 m/s) to minimize erosion-corrosion effects and relatively large fluid channel sizes (>=1 mm) to prevent clogging. The power module concept was fabricated, and experiments were conducted to measure its thermal performance. Direct current was used to power the module devices, and junction temperatures were measured via device temperature-sensitive parameters. The experimental results were found to be in good agreement with model predictions (within 2%) and yielded junction-to-fluid thermal resistance values as low as about 15 mm2 K/W at relatively low pumping power values. The results demonstrate the improved performance associated with jet impingement cooling and represent an improvement over existing channel-flow-type cold plates, which can enable improvements to power density and reliability.
Long-term exposure to Pb 2+ can cause irreversible damage to the nervous, cardiovascular, and reproductive systems. Therefore, developing a fast and sensitive detection system capable of monitoring minuscule concentrations of Pb 2+ is essential. In this study, we demonstrated a fully portable sensor system enabling rapid, sensitive, and real-time monitoring of Pb 2+ . The sensor system adopted the remote-gate field-effect transistor (RGFET) detection scheme and was easy to operate, even for non-experts. The sensor system comprised two printed circuit boards (PCBs): a sensor PCB with a remote-gate electrode and an analyzer PCB with a metal-oxide-semiconductor field-effect transistor (MOSFET) transducer and peripheral electronics to manage sensor signals. To achieve a high sensitivity for Pb 2+ , we utilized graphene ink drop-casted on the sensor PCB as a sensing membrane. The graphene film was easy to deposit and remove, enabling the sensor PCB to be reused multiple times. The sensor system was further linked to a smartphone application that instantly monitors the sensor response, allowing for rapid point-of-use detection. The sensor exhibited a high sensitivity of 21.7% when the limit of detection (LOD) value of 1 nM (∼0.2 ppb) was detected, and the typical detection time for each sample was approximately 60 seconds. This portable sensor system advances sensing technologies and could potentially supplement expensive, laborious conventional sensing equipment.
In this work, p-channel 4H-SiC MOSFETs were fabricated and analyzed at high temperature. It is demonstrated that nitridation of the gate oxide enables enhancement mode operation in these devices. Nitrogen incorporation at the 4H-SiC/SiO2 interface by nitric oxide annealing reduces the interface trap density energetically located in the lower half of the 4H-SiC bandgap, resulting in viable high temperature p-channel devices. In the 27–300 °C temperature range, the threshold voltage decreases with increasing temperature, consistent with the reduction of occupied interface traps at higher temperatures. The hole channel mobility is weakly temperature dependent under strong inversion conditions. Hall measurements support that above the threshold voltage, the mobility is limited by surface roughness scattering. In weaker inversion, the channel conductivity is limited by interface hole trapping and Coulomb scattering. In addition, high temperature bias stress measurements confirm a temperature activated hole trapping under negative gate bias, which requires further investigations.
In this study, electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO 2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO 2 boundary. The interface traps observed are P b0 and P b1 centers, which are silicon dangling bond defects. The ratio of P b0 /P b1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E' oxide defects near the Si/SiO 2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.
Organic Direct-Bonded-Copper (ODBC) is a novel packaging technology for power modules which allows higher flexibility in layout design. In this work, a set of rapid prototyping techniques are developed for ODBC modules based on a polyimide dielectric material. These techniques enable fast and low-cost fabrication of modules with 3-Dimensional (3D) layout features. An example half-bridge (HB) silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) module is designed and prototyped using the proposed techniques aiming at ultra-low power loop inductance. Finite element analysis (FEA)-circuit co-simulations results and experimental results validate an approximately 0.71nH power loop inductance for the example module design.
This paper is focused on a transformer-isolated quadruple active bridge (QAB) dc-dc converter loaded by three full-bridge dc-ac inverters. The QAB functions as a "DC trans-former" (DCX) in the dc-to-three-phase ac module. The QAB outputs provide time-varying power at twice the line frequency, which presents challenges in maintaining zero voltage switching (ZVS) on the secondary sides during low-power portions of the line cycle. It is shown how ZVS can be achieved in a phase, even at zero-power transfer, using a relatively small circulating current provided by the magnetizing inductance of the high-frequency transformer. The approach is particularly effective in high-voltage applications using SiC MOSFETs, where reductions in switching loss outweigh additional conduction losses due to the circulating currents. A detailed analysis of ZVS switching waveforms at the zero power transfer is presented, including effects of nonlinear device capacitances. Analytical expressions are given for the optimal values of the magnetizing inductance and dead times of the QAB primary and secondary bridges. The approach is verified by experimental results on a 600 V, 4 kW prototype, demonstrating greater than 98.5% efficiency from 1 kW to 4 kW, with a peak efficiency of 99.0%. Compared to conventionally operated prototype, a 54% reduction in total loss is achieved at rated power.
The surge voltage induced by lightning will generate an inrush current in a grid-connected converter. It may not be large in Si-based converters because of the large grid side inductive filter. However, for SiC-based multi-level converters, the inrush current could be very large due to the small filter inductance, which is selected based on the current harmonic consideration. Most previous work focuses on system-level lightning protection while the converter-level impact, especially the internal components of the converter, is rarely discussed. This paper presents the analysis of the impact of the lightning surge on a 10 kV SiC MOSFET-based 13.8 kV three-phase four-wire grid-connected converter. The IEEE arrester model and the combined wave generator model in IEC 61000-4-5 standard are used to evaluate the inrush current, DC-link overvoltage, and component-to-ground potential of the converter. Analysis and simulation results have been provided to demonstrate the impact of lightning on the grid-connected converter. It is found that large inrush current occurs due to the small filter inductance, and the neutral-to-ground impedance impacts both the inrush current and the neutral point-to-ground potential.
—The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.
A four-quadrant switch (FQS) blocks either polarity voltage and controls current flow in both directions. Unlike voltage-source converters, in which two-quadrant switches operate over a narrow voltage range, four-quadrant switches are required to operate over a wide range of both voltage and current in applications such as matrix converters and current-source converters. Furthermore, matrix converters require multi-step commutation schemes compared to two-step schemes for current-bidirectional switch based voltage-source converters and voltage-bidirectional switch based current-source converters. This paper provides a generalized overview of commutation schemes used for two and four quadrant switches based two-level commutation cells, identifies comparison indices for FQS commutation schemes, and discusses the need for adaptive commutation-step times for wide voltage and current variation applications. Also, the static and dynamic characteristics of 1.2 kV rated FQS implementations utilizing commercial SiC MOSFETs from four different manufacturers and novel monolithic SiC BiDirectional Field Effect Transistor (BiDFET) have been reported.
This paper presents a loss-optimized Triple Phase-Shift (TPS) switching strategy for Dual-Active Bridge (DAB) based converters. The proposed strategy considers minimizing total converter loss with respect to minimizing device rms cur-rents, enabling Zero-Voltage Switching (ZVS) turn-on of devices and accurate control of device turn-off current. A model for switching currents is presented, followed by a loss model and optimization strategy. A 1.3kV/100kW prototype based on SiC MOSFETs was used in this work and experimental results up to 10kW show the proposed TPS strategy to be more efficient for operation.
The accuracy of states measured from simulation of a dual-active bridge (DAB) converter with an open-loop controller has been used for comparing simulation software and algorithms. The accuracy of the measured states is sensitive to simulation settings and parameters chosen. In this paper, the simulation of the DAB converter with open-loop control is run in the MATLAB/Simscape Electrical, PLECS, and PSCAD software environments, with various simulation settings. The simulation results are also compared with a new simulation algorithm proposed for DAB simulations. Different simulation settings are evaluated, including different solver types, operating conditions, and the on-state resistance values of the MOSFET switches. The simulation results are compared with the theoretical calculations. It is shown that unexpected divergence and DC offset may occur in some cases. This paper provides guidelines to simulate the DAB converter with open-loop control.
Smart inverters exchange information with other devices through a shared communication link, making the inverters more prone to receive harmful commands from external parties. This erroneous data can be received due to an anomaly in the system, such as a device fault, unintentional utility operator action, or a cyber-attack. In this paper, a device-level self-security strategy is implemented using reference models for a grid-interactive inverter to examine the incoming power setpoints, detect the anomalies, and protect the system accordingly. The PQ setpoints received from the utility supervisory controller are autonomously examined using the inverter’s normal and stable operating regions before engaging the setpoints to the inverter’s local controller. Grid parameters are estimated in real-time during the examination process. The efficacy of the self-security algorithm is tested using a three-phase 3-kVA SiC-MOSFET inverter and a 12-kW NHR 9410 regenerative grid emulator. The results verify that the proposed method can detect harmful PQ setpoints that can cause abnormal or unstable inverter operation.
Smart inverters connected to a communication network are vulnerable to various anomalies in the form of cyberattacks. In this paper, a self-security approach is implemented using the digital twin concept for smart inverters. The digital twin is formed using the inverter’s dynamic model. Then, the incoming setpoints are autonomously examined using the digital twin, and only the safe setpoints are engaged to the inverter’s local controller. This paper demonstrates the details of the self-security algorithm and how the inverter’s digital twin is formed. In particular, the stable and unstable operation region is experimentally verified by changing the power setpoints engaged to the local controller, using a laboratory setup including a three-phase 1.5-kVA SiC-MOSFET inverter and a 12-kW NHR 9410 regenerative power grid emulator. The results demonstrate that the digital twin model can potentially protect inverters from abnormal operation by examining the incoming commands (new setpoints) using the inverter’s digital twin before engaging the setpoints to the local controller.
The auxiliary resonant commutated pole (ARCP) is being used to achieve zero voltage switching (ZVS) of power switches for improved efficiency and/or to reduce dv/dt at the switch node for better electromagnetic interference (EMI) performance and overall system reliability. This paper shows how an ARCP circuit can be used in a wireless power transfer system to achieve ZVS. Detailed analysis of ARCP circuit operation is presented to determine the requirements for achieving ZVS in the main switches of a wireless electric vehicle charging system. Based on this analysis, a design algorithm is developed to optimize the design of the ZVS assisting circuit components. The designed ARCP achieves soft switching of the MOSFETs in the primary inverter of an 85 kHz, 10 kW series-series compensated, stationary wireless power transfer system.