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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,243 records · Page 69
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Measurement of fault latency in a digital avionic miniprocessor

The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are presented. The failure detection coverage of comparison-monitoring and a typical avionics CPU self-test program was determined. The specific tasks and experiments included: (1) inject randomly selected gate-level and pin-level faults and emulate six software programs using comparison-monitoring to detect the faults; (2) based upon the derived empirical data develop and validate a model of fault latency that will forecast a software program's detecting ability; (3) given a typical avionics self-test program, inject randomly selected faults at both the gate-level and pin-level and determine the proportion of faults detected; (4) determine why faults were undetected; (5) recommend how the emulation can be extended to multiprocessor systems such as SIFT; and (6) determine the proportion of faults detected by a uniprocessor BIT (built-in-test) irrespective of self-test.

Mcgough, J. G.↗
NASA NTRS1983

Distributed multiport memory architecture

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Kohl, W. H.↗
NASA NTRS1983

High-performance K-band GaAs power field-effect transistors prepared by molecular beam epitaxy

The maturity of the molecular beam epitaxy (MBE) technique for preparing device quality GaAs material for microwave applications is demonstrated by the excellent performance characteristics of K-band GaAs power field-effect transistors (FETs) fabricated on the MBE wafers. An output power of 710 mW with 4.5-dB gain and 17.7 percent power-added efficiency was achieved at 21 GHz with a 1.26-mm gate width pi-gate device. A similar device with a 0.56-mm gate width produced an output power of 320 mW with 5.0-dB gain and 26.6 percent power-added efficiency at 21 GHz. These are the best results yet reported to date for GaAs power FETs operated in the K-band frequency range.

Saunier, P.↗
NASA NTRS1984

0.5 W 2-21 GHz monolithic GaAs distributed amplifier

A novel circuit concept to reduce the gate loss using series capacitors on the gate feeding lines has been implemented for a distributed amplifier design. It has significantly increased the gate width of the amplifier with a resultant increase of the broadband output power and efficiency. A monolithic GaAs distributed amplifier using 6 x 300-micron FETs has achieved a record output power of 0.5 W over the 2 to 21 GHz frequency band with at least 4 dB gain. The power-added efficiency was 14 percent. The linear gain was 5 plus or minus 1 dB over the same frequency band.

Kim, B.↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS1985

HEMT 60 GHz amplifier

A high electron mobility transistor (HEMT) amplifier has been fabricated which exhibits 7.5 dB gain at 61 GHz. This result was obtained with a quarter-micrometre gate-length depletion-mode HEMT. Reduction of source-gate resistance and gate length are primarily responsible for this performance. The letter describes the materials and device processing technology developed for fabricating these devices.

Berenz, J.↗
NASA NTRS1986

Dc and microwave characteristics of a high current double interface GaAs/InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistor

Extremely large current double interface GaAs/In(0.15)Ga(0.85)As/Al(0.15)Ga(0.85)As pseudomorphic modulation-doped field-effect transistors (MODFET's) grown by molecular beam epitaxy were achieved. The 1-micron gate devices studied have peak current levels (430 mA/mm at 300 K and 483mA/mm at 77 K) roughly one and a half to two times that found in single interface pseudomorphic MODFET's. These devices also retain high transconductances over a broad range of gate voltage, peaking at 312 mS/mm at 300 K and 362 mS/mm at 77 K. Excellent microwave performance is also obtained with a maximum frequency of oscillation (f-max) of 37 GHz and a current gain cut-off frequency of as high as 23 GHz at 300 K. An output power level of 14 dBm (1 dB gain compression) was obtained at 6 GHz for a 290-micron gate width. This double interface single quantum well MODFET may be of great importance in millimeter wave power amplifiers.

Henderson, T.↗
NASA NTRS1987

CMOS Clock Synchronizer

Circuit synchronizes clock and gate signals within one-quarter of clock cycle. Clock synchronizer with one-quarter-cycle skew constructed from three flip-flops, three NAND gates, and inverter. In addition gate signal to which clock synchronized, circuit requires square-wave input at twice desired clock frequency.

Kepp, R. B.↗
NASA NTRS1985

High speed photography, videography, and photonics III; Proceedings of the Meeting, San Diego, CA, August 22, 23, 1985

Papers are presented on the picosecond electronic framing camera, photogrammetric techniques using high-speed cineradiography, picosecond semiconductor lasers for characterizing high-speed image shutters, the measurement of dynamic strain by high-speed moire photography, the fast framing camera with independent frame adjustments, design considerations for a data recording system, and nanosecond optical shutters. Consideration is given to boundary-layer transition detectors, holographic imaging, laser holographic interferometry in wind tunnels, heterodyne holographic interferometry, a multispectral video imaging and analysis system, a gated intensified camera, a charge-injection-device profile camera, a gated silicon-intensified-target streak tube and nanosecond-gated photoemissive shutter tubes. Topics discussed include high time-space resolved photography of lasers, time-resolved X-ray spectrographic instrumentation for laser studies, a time-resolving X-ray spectrometer, a femtosecond streak camera, streak tubes and cameras, and a short pulse X-ray diagnostic development facility.

Ponseggi, B. G.↗
NASA NTRS1987

Implementation of optical interconnections for VLSI

This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

Wu, Wennie H.↗
NASA NTRS1988

MOSFET Electric-Charge Sensor

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Robinson, Paul A., Jr.↗
NASA NTRS1987

Error propagation in a digital avionic mini processor

A methodology is introduced and demonstrated for the study of error propagation from the gate to the chip level. The importance of understanding error propagation derives from its close tie with system activity. In this system the target system is BDX-930, a digital avionic multiprocessor. The simulator used was developed at NASA-Langley, and is a gate level, event-driven, unit delay, software logic simulator. An approach is highly structured and easily adapted to other systems. The analysis shows the nature and extent of the dependency of error propagation on microinstruction type, assembly level instruction, and fault-free gate activity.

Lomelino, Dale L.↗
NASA NTRS1987

CMOS detector cells for holographic optical interconnects in microcircuits

This paper reports on the characterization of CMOS detectors for holographic optical interconnects in micro circuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate the identification of the sample area under investigation. An isolated photodiode and load circuit has been characterized to determine responsivity, response time, and light spot positioning effects. The threshold of optical gate cells incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 microW light input. Threshold power was 0.5 microW light input.

Wu, W. H.↗
NASA NTRS1988

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.↗
NASA NTRS1988

A CMOS matrix for extracting MOSFET parameters before and after irradiation

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Blaes, B. R.↗
NASA NTRS1988

Get-Away tether experiment - Experimental plans

The experimental capabilities of the Get-Away Tether Experiment (GATE) are presented and a series of demonstration mission are proposed. The GATE is a free-flying tether system that will develop or demonstrate technology in the areas of tether dynamics (deployment and stabilization, retrieval, stationkeeping, and severance), tether electrodynamics, micrometeor hazards to tethers, and disturbance rejection. The system consists of two subsatellites connected by 1 km of tether. The free-flying system is ejected from the Orbiter via a Getaway Special (GAS) canister. Two dynamics missions are profiled along with a description of electrodynamic mission capabilities. The dynamic interactions of the end body and tether may be observed from the Orbiter or from an on-board video tracking system. Hence, GATE provides a unique, low cost capability to demonstrate various tether technologies, and address critical design and safety issues associated with future tether applications. An assessment of the significant measurable parameters and associated instrumentation is given. Future work and system development projection schedules are also outlined.

Greene, Michael↗
NASA NTRS1990

Voltage-Boosting Driver For Switching Regulator

Driver circuit assures availability of 10- to 15-V gate-to-source voltage needed to turn on n-channel metal oxide/semiconductor field-effect transistor (MOSFET) acting as switch in switching voltage regulator. Includes voltage-boosting circuit efficiently providing gate voltage 10 to 15 V above supply voltage. Contains no exotic parts and does not require additional power supply. Consists of NAND gate and dual voltage booster operating in conjunction with pulse-width modulator part of regulator.

Trump, Ronald C.↗
NASA NTRS1988

The 30-GHz monolithic receive module

The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed.

Bauhahn, P.↗