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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Engineers within the commercial and aerospace industries are using trade-off and risk analysis to aid in reducing spacecraft system cost while increasing performance and maintaining high reliability.
Piggy-back method of packaging integrated circuits will increase packaging density and design flexibility. It will also eliminate interconnection leads between the die and associated inductances, and thus increase the attainable frequency response of the circuit.
Large scale integration and metal oxide semiconductor microelectronic testing techniques including combinatorial, sequential, functional, and parametric methods
Large scale integration microelectronic wafer and package testing including parametric and functional tests of combinatorial and sequential logic circuits
Vacuum evaporated films of Au, Pt, and Au-on-Pt on glass substrates after heat treatment
In the proposed modeling approach, when any of the essential key factors are not known initially, they can be approximated in various ways with a known impact on the accuracy of the final predictions. For example, on any program where reliability predictions are started at interim states of project completion, a-priori approximate estimates of the key factors are established for making preliminary predictions. Later these are refined for greater accuracy as subsequent program information of a more definitive nature becomes available. Specific steps to develop, validate and verify these new models are described.
Brief discussions of the techniques used to make dielectric and metal thin film depositions for monolithic circuits are presented. Silicon nitride deposition and the properties of silicon nitride films are discussed. Deposition of dichlorosilane and thermally grown silicon dioxide are reported. The deposition and thermal densification of borosilicate, aluminosilicate, and phosphosilicate glasses are discussed. Metallization for monolithic circuits and the characteristics of thin films are also included.
Data accumulated during 4 years of research and evaluation of ceramic chip capacitors, ceramic carrier mounted active devices, beam-lead transistors, and chip resistors are presented. Life and temperature coefficient test data, and optical and scanning electron microscope photographs of device failures are presented and the failure modes are described. Particular interest is given to discrete component qualification, power burn-in, and procedures for testing and screening discrete components. Burn-in requirements and test data will be given in support of 100 percent burn-in policy on all NASA flight programs.
Irradiation of several low power circuit elements by Co-60 gamma radiation, low and high energy electrons, and neutrons is discussed. The bipolar circuits were SE480 Q NAND gate, and a micropower frequency divider was used in electronic wrist watches. The MOS device was a dual p-channel MOSFET.
The use of aluminum beam lead devices in hybrid circuits is described by modification of existing processing equipment. Principles, procedures, and methods of application of Al beam lead devices are discussed in terms of processing the devices onto hybrids.
The initial results of a study directed to the task of selecting suitable evaluation tests which can form the basis for guidelines for electrically insulated adhesives are given. The properties of adhesives considered to be of major importance for the proposed application are enumerated, with brief comments. Specific tests to determine the chemical and electrolytic corrosivity of adhesives to commonly used metallization systems, their long-term outgassing after cure, and their bond strengths under a variety of conditions are defined and discussed in detail.
Scanning electron microscopes are used to determine both user-induced damages and manufacturing defects subtle enough to be missed by conventional light microscopy. Method offers greater depth of field and increased working distances.
Ceramic multilayer circuitry results from the sequential build-up of two or more layers of pre-determined conductive interconnections separated by dielectric layers and fired at an elevated temperature to form a solidly fused structure. The resultant ceramic interconnect matrix is used as a base to mount active and passive devices and provide the necessary electrical interconnection to accomplish the desired electrical circuit. Many methods are known for developing multilevel conductor mechanisms such as multilayer printed circuits, welded wire matrices, flexible copper tape conductors, and thin and thick-film ceramic multilayers. Each method can be considered as a specialized field with each possessing its own particular set of benefits and problems. This design guide restricts itself to the art of design, fabrication and assembly of ceramic multilayer circuitry and the reliability of the end product.
Differential thermal expansion was shown to be responsible for many observed failures in ceramic chip capacitors mounted on alumina substrates. It is shown that the mounting techniques used in bonding the capacitors have a marked effect upon the thermally induced mechanical stress and thus the failure rate. A mathematical analysis was conducted of a composite model of the capacitor-substrate system to predict the magnitude of thermally induced stresses. It was experimentally observed that the stresses in more compliant bonding systems such as soft lead tin and indium solders are significantly lower than those in hard solder and epoxy systems. The marked dependence upon heating and cooling rate was proven to be a determining factor in the prediction of failure solder systems. It was found that the harder or higher melting solders are less susceptible to thermal cycling effects but that they are more likely to fail during initial processing operations. Strain gage techniques were used to determine thermally induced expansion stresses of the capacitors and the alumina substrates. The compliance of the different bonding mediums was determined. From the data obtained, several recommendations are made concerning the optimum bonding system for the achievement of maximum reliability.
Engineering design guidelines enumerate and briefly describe selected adhesive properties. General review of polymeric types of adhesives is included and major types of commercially available adhesives specifically designed for microelectronic use are identified.
An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.
A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.