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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Scalable low-loss cryogenic packaging of quantum memories in CMOS-foundry processed photonic chips

Optically linked solid-state quantum memories such as color centers in diamond are a promising platform for distributed quantum information processing and networking. Photonic integrated circuits (PICs) have emerged as a crucial enabling technology for these systems, integrating quantum memories with efficient electrical and optical interfaces in a compact and scalable platform. Packaging these hybrid chips into deployable modules while maintaining low optical loss and resiliency to temperature cycling is a central challenge to their practical use. We demonstrate a packaging method for PICs using surface grating couplers and angle-polished fiber arrays that is robust to temperature cycling, offers scalable channel count, applies to a wide variety of PIC platforms and wavelengths, and offers pathways to automated high-throughput packaging. Using this method, we show optically and electrically packaged quantum memory modules integrating all required qubit controls on chip, operating at millikelvin temperatures with <3 dB losses achievable from fiber to quantum memory for the TE 0 mode at a wavelength of 737 nm.

Bernson, Robert [Tyndall National Institute, Cork ↗
DOE OSTI2025

Telecom-to-visible quantum frequency converter on a silicon nitride chip

Quantum frequency conversion serves a key role in the realization of hybrid quantum networks by interfacing between wavelength-incompatible platforms. Here we present what is believed to be the first quantum frequency converter connecting visible and telecom domains on a silicon nitride (SiN) chip, using Bragg-scattering four-wave mixing to upconvert heralded single photons from 1260 to 698 nm, which covers a 192 THz span. We examine the noise sources in SiN and devise approaches to suppress noise photons at the source and target frequencies to enable measurements at the single-photon level. We demonstrate an on-chip conversion efficiency of 5% in photon flux and describe design modifications that can be implemented to significantly improve it. Our results pave the way for the implementation of complementary metal-oxide-semiconductor (CMOS)-compatible devices in quantum networks.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

Beam test results for the Endcap Timing ReadOut Chip (ETROC2) for the CMS ETL upgrade

The Endcap Timing ReadOut Chip (ETROC) for the Compact Muon Solenoid (CMS) Minimum ionizing particle Timing Detector (MTD) is designed to process Low Gain Avalanche Diode (LGAD) signals with a time resolution of 40-50ps per hit, with 30-35 ps per charged particle using two layer detector. The ETROC2, is the first full size (16x16 pixels) and full functionally design that has been tested in hadron and electron beams at CERN and DESY (Sep 2023 - June 2024). Precision timing studies at these test beams are done using a self-referential beam telescope composed of up to 4 layers/chips. This talk describes the ETROC2 beam telescope and summarizes the performance of the ETROC2 chips bump-bonded to (16x16) Fondazione Bruno Kessler (FBK) and Hamamatsu Photonics K.K. (HPK) LGAD sensors using results from recent test beams. The experiences and lessons learned during the course of these test beams are also detailed in this talk.

Safdari, Murtaza↗
DOE OSTI2024

The Single Event Error (SEE) test and analysis of the CMS Endcap Timing Layer readout chip

The ETROC2, the first full size and full functionality prototype chip for the CMS Endcap Timing Layer readout, is strategically designed to meet the SEE immunity requirements of detector operation with the low power constraint. The triplicated periphery and pixel I2C configuration registers are designed with self-correction feature. The pixel readout control is centralized in the global readout and fully triplicated. The pixel readout is not triplicated, instead protected with power-efficient one-bit correction Hamming code. The TMR protection of the on-pixel threshold calibration can be turned off allowing the detection of the beam spot during the beam test by checking the bit-flips of the internal memory cells. In the initial proton beam test in January 2024, the chip readout process did not hang throughout the tests. The Hamming code correction strategy works because the error corrected TDC data were observed in the data frames. The error-injection simulation is performed to analy ze the small number of bit-flips in the configuration registers. We also performed SEE testing with a heavy ion beam in April and the data analysis is ongoing. The detailed design on the SEE immunity and the testing as well as simulation results will be presented, including follow-up SEE testing results in May and June 2024.

Gong, Datao↗
DOE OSTI2025

Shear Assisted Processing and Extrusion of Magnesium Alloy Machining Chips

The Pacific Northwest National Laboratory (PNNL) utilized Shear Assisted Processing and Extrusion (ShAPE) to convert magnesium alloy machining chips directly into wrought material. PNNL fabricated 0.25” and 0.50” round rod from cold compacted briquettes pressed from dry-machined chips by Loukus Technologies. The alloy composition is proprietary and protected by a Materials Transfer Agreement (MTA) between PNNL and Loukus. Extrusions were fabricated using the ShAPE 2.0 machine, tooling, and process. PNNL is evaluating tensile properties per ASTM E8 and microstructure for grain size, texture, and porosity using Scanning Electron Microscopy (SEM) and Electron Backscatter Diffraction (EBSD). Tensile properties and microstructure results were not available at the time of writing this document. Extruded rods have also been sent to Loukus for evaluation.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Automated Detection of Qubit Structures on Quantum Chips

In this study, YOLO (You Only Look Once), a well-known object detection and image segmentation model, is used to detect qubits on a quantum chip. The model is trained by exposing it to various images of objects of interest and by setting various training parameters to allow the model to learn in unconventional conditions. We were able to provide the model with numerous images of qubits and various prominent features of note located on a qubit. We then created a simple GUI to display the model's live detections that would be integrated with the SEMs. This allowed us to create various functions such as auto-imagery of the qubits across a chip, auto-focusing, auto-contrasting, automatic staging, and directional corrections, enabling users to scan and analyze qubit surfaces in a fast and effective manner.

Perjuste, Ruth [Wellesley Coll.]↗
NASA NTRS1969

Improved method of dicing integrated circuit wafers into chips

Method employing a pressure chamber is used for dicing semiconductor single-crystal wafers, containing integrated circuits, into small chips along pre-scribed lines. Uniform bending of the scribed wafer over the convex surface of a perforated hemisphere, breaks it cleanly into individual chips without damaging the circuits.

Litant, I.↗
NASA NTRS1972

Development of chip passivated monolithic complementary MISFET circuits with beam leads

The results are presented of a program to demonstrate the processes for fabricating complementary MISFET beam-leaded circuits, which, potentially, are comparable in quality to available bipolar beam-lead chips that use silicon nitride passivation in conjunction with a platinum-titanium-gold metal system. Materials and techniques, different from the bipolar case, were used in order to be more compatible with the special requirements of fully passivated complementary MISFET devices. Two types of circuits were designed and fabricated, a D-flip-flop and a three-input NOR/NAND gate. Fifty beam-leaded chips of each type were constructed. A quality and reliability assurance program was performed to identify failure mechanisms. Sample tests and inspections (including destructive) were developed to measure the physical characteristics of the circuits.

Ragonese, L. J.↗
NASA NTRS1973

Laser scanner for testing semiconductor chips

Individual ''fingerprint'' signals are produced when system photoexcites chips. ''Fingerprints'' are analyzed for characteristics associated with defects, including many not visible to the naked eye. Electromagnetic radiation photogenerates free electrons and holes in semiconductor chip. These carriers produce electrical signals at terminals. Signals vary depending on what defects are present.

Hall, T. C.↗
NASA NTRS1980

Azimuth correlator design for IC chip

Azimuth correlator circuit synthetic-aperature radar (SAR) is designed for single integrated circuit (IC) chip. Azimuth correlator modules constructed with sets of such chips could make real-time signal processing possible. Primary advantages are realized in areas of weight and power requirement reductions.

Tyree, V. C.↗
NASA NTRS1978

Indium antimonide infrared CCD linear imaging arrays with on-chip preprocessing

A description is presented of the fabrication of a new InSb CCD chip based on an improved process which eliminates the limitations inherent with the earlier techniques. This process includes planar junction formation and an aluminum and SiO2 material system which is amenable to state-of-the-art chemical and plasma delineation techniques. Further, the new chip integrates for the first time in monolithic format InSb IR detectors with an InSb CCD. The reported experiments represent the first operation of an InSb infrared CCD array. In addition to fuller characterization of the 20-element charge-coupled infrared imaging device, several factors which influence device performance are currently being addressed. These include surface state density, the CCD output circuit, and storage time (dark current).

Thom, R. D.↗
NASA NTRS1980

Single-chip microcomputer application in high-altitude balloon orientation system

This paper describes the application of a single-chip microcomputer in a high-altitude balloon instrumentation system. The system, consisting of a magnetometer, a stepping motor, a microcomputer and a gray code shaft encoder, is used to provide an orientation reference to point a scientific instrument at an object in space. The single-chip microcomputer, Intel's 8748, consisting of a CPU, program memory, data memory and I/O ports, is used to control the orientation of the system.

Lim, T. S.↗
NASA NTRS1982

The VLSI design of a single chip Reed-Solomon encoder

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

Truong, T. K.↗
NASA NTRS1983

Programming substructure computations for elliptic problems on the CHiP system

A number of studies have been conducted with the aim to apply parallel computation to problems associated with solving finite element equations arising in structural mechanics and fluid dynamics. These studies have provided many important results. The present investigation is concerned with a set of experiments designed to test two ideas, including configurability and substructuring. The considered algorithms and tests are intended for implementation on the Configurable, Highly Parallel (CHiP) family of architecture described by Snyder (1982). The ChiP computer is composed of homogeneous processing elements (PEs) placed at regular intervals in a lattice of programmable switches. Two examples of the role of configurability and substructuring for simple iterative algorithms are considered, giving attention to conjugate gradient iterations, and tridiagonal systems of equations.

Gannon, D.↗
NASA NTRS1985

Designing Test Chips for Custom Integrated Circuits

Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

Buehler, M. G.↗
NASA NTRS1985

High-voltage solar-cell chip

Integrated circuit technology has been successfully applied to the design and fabrication of 0.5 x 0.5-cm planar multijunction solar-cell chips. Each of these solar cells consisted of six voltage-generating unit cells monolithically connected in series and fabricated on a 75-micron-thick, p-type, single crystal, silicon substrate. A contact photolithic process employing five photomask levels together with a standard microelectronics batch-processing technique were used to construct the solar-cell chip. The open-circuit voltage increased rapidly with increasing illumination up to 5 AM1 suns where it began to saturate at the sum of the individual unit-cell voltages at a maximum of 3.0 V. A short-circuit current density per unit cell of 240 mA/sq cm was observed at 10 AM1 suns.

Kapoor, V. J.↗
NASA NTRS1985

A VLSI single chip (255,223) Reed-Solomon encoder

A description of a working single chip implementation of a Reed-Solomon encoder. The code used is the Consultative Committee on Space Data Systems (CCSDS) standard (255,223) code. The architecture that leads to this single very large scale integration chip design makes use of a bit-serial finite field multiplication algorithm of E. R. Berlekamp.

Deutsch, L. J.↗