SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Equivalent circuit and modified and approximate models for metal oxide semiconductor-field effect transistor devices, and adaptability to computerized circuit design
Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decisionmaking ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline/polyethylene oxide (PANi/PEO) nanofibers are of interest because they have electrical conductivities that can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain. At the NASA Glenn Research Center, we have observed field effect transistor (FET) behavior in electrospun PANi/PEO nanofibers doped with camphorsulfonic acid. The nanofibers were deposited onto Au electrodes, which had been prepatterned onto oxidized silicon substrates. The preceding scanning electron image shows the device used in the transistor measurements. Saturation channel currents are observed at surprisingly low source/drain voltages (see the following graph). The hole mobility in the depletion regime is 1.4x10(exp -4)sq cm/V sec, whereas the one-dimensional charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx.10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating one-dimensional polymer FET's.
A multistage GaAs FET power amplifier, employing cascaded balanced stages using state-of-the-art 1/4, 1/2, and 1 watt devices, has been developed. A linear gain of 30 dB with 1.25 watts output has been achieved over a 17.7 to 19.4 GHz frequency band. The development and performance of the amplifier and its components are discussed.
We have successfully fabricated, tested, and operated a digital image tube consisting of a magnetically focused image intensifier tube in which a self-scanned linear array of 1024 silicon photodiodes operating in the EBS mode serves as the photoelectron image detector, amplifier, and intermediate image storage device. Integral on-chip MOS shift registers driven by an external clock sequentially interrogate the photodiodes through MOS FET multiplex switch arrays. Each output frame is a sequence of 256 analog pulses on each of four video lines. Laboratory and observing tests show that the output signal is photoelectron shot noise limited over at least a range of 1-100,000 detected photoelectrons per picture element, indicating that single photon detection is achieved. High-resolution astronomical spectroscopy has been carried out in the coude spectrograph of the 2.7-m telescope at McDonald Observatory. Examples are shown.
A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.
A high-performance MODFET structure grown by MBE with the incorporation of a single quantum well In(0.15)Ga(0.85)As layer for the transport of two-dimensional electron gas has been critically examined for its thermal stability at 80 K and low-frequency noise form 0.01 to 10 to the 8th Hz. Experimental results indicate that the behavior of this device in both these respects is much superior when compared with the same behavior of conventional MODFETs. A maximum low-field carrier mobility of 29,000 sq cm/s at 80 K and an average carrier saturation velocity of 2 x 10 to the 7th cm/s at 300 K in a 1-micron gate device clearly indicate that the quality of the pseudomorphic quantum well (InGaAs) layer is either comparable or better than that of the usual GaAs buffer layer. The deep level spectra, obtained through photo-FET measurements, and the low-frequency noise spectra at different temperatures obtained for the new pseudomorphic and conventional MODFET's have clearly indicated that contributions from various deep levels present in the new structure are significantly reduced.
This paper describes a 256 x 256 HgCdTe hybrid focal plane with a 0.9- to 2.6-micron spectral range. The silicon FET switch multiplexer (mux) is based on previous hybrid work with a 128 x 128 Reticon mux. The high-density device described has a 40-micron pixel pitch vs 60-micron pixel pitch for the 128 x 128 devices. A read noise of about 1,000 e(-) has been obtained on developmental hybrid structures, along with full well capacities of about 1 x 10 to the 6th e(-). Preliminary device characterization for the 256 x 256 device, along with the first low-background astronomy test results for the 128 x 128 devices, will be presented.
Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.
In the case of modern infrared focal planes, one of the major problems is related to the noise contribution of the cooled, impedance-matching device used as the preamplifier stage in the detector electronics system. An ideal preamp device should have the low-noise advantages of a buried-channel device and operate isothermally with the low-temperature detector array. The Ge JFET might provide this ideal device. A testing program with Ge JFETs is discussed. It is concluded that germanium JFETs offer an attractive alternative for cryogenic preamplifier designs. They operate well with high transconductance and low noise at LHe temperatures. It is believed that these devices point the way for the development of large, integrated-array, long wavelength, infrared focal planes which incorporate germanium detectors, germanium load resistors, and germanium preamplifiers within the same monolithic structure.
During the contract period an AsCl3 epitaxial system used to provide buffer layers for FET structures was constructed. A submicron lithographic processes using deep U.V. techniques was developed and, employing these techniques, a working .5 micron gate device was produced. In addition, the development of submicron mixer diodes continued. The gettering of substrates of a technique to improve the mobility of ionimplantated layers was investigated. The result of this experiment showed a correlation between improved hall mobilities and gettered substrates. Finally, several theoretical studies are reported.
This letter reports the performance of a novel single-stage W-band amplifier fabricated utilizing flip-chip bump-bonding. We have bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) device onto a separately fabricated passive circuit having a GaAs substrate.
The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.
A high-frequency equivalent-circuit model of a GaAs dual-gate FET and analytical expressions for the input/output impedances, transconductance, unilateral gain, and stability factor are presented. It is found that the gain of a dual-gate FET is higher than of a single-gate FET at low frequency but decreases faster as frequency increases because of the capacitive shunting effect of the second gate. A dual-gate power FET suitable for variable-gain-amplifier applications up to K-band has been developed. At 10 GHz, a 1.2-mm-gatewidth device has achieved an output power of 1.1 W with 10.5-dB gain and 31-percent power-added efficiency. At 20 GHz, the same device delivered an output power of 340 mW with 5.3-dB gain. At K-band, a dynamic-gain control range of up to 45 dB was obtained with an insertion phase change of no more than + or 2 degrees for the first 10 dB of gain control.
Two modules of gallium-doped germanium (Ge:Ga) infrared detectors with integrated multiplexing readouts and supporting drive electronics were designed and tested. This development investigated the feasibility of producing two-dimensional Ge:Ga arrays by stacking linear modules in a housing capable of providing uniaxial stress for enhanced long-wavelength response. Each module includes 8 detectors (1x1x2 mm) mounted to a sapphire board. The element spacing is 12 microns. The back faces of the detector elements are beveled with an 18 deg angle, which was proved to significantly enhance optical absorption. Each module includes a different silicon metal-oxide semiconductor field effect transistor (MOSFET) readout. The first circuit was built from discrete MOSFET components; the second incorporated devices taken from low-temperature integrated circuit multiplexers. The latter circuit exhibited much lower stray capacitance and improved stability. Using these switched-FET circuits, it was demonstrated that burst readout, with multiplexer active only during the readout period, could successfully be implemented at approximately 3.5 K.
Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.
A new commercial-off-the-shelf (COTS) gate driver designed to drive both the high-side and the low-side enhancement-mode GaN FETs, National Semiconductor's type LM5113, was evaluated for operation at temperatures beyond its recommended specified limits of -40 C to +125 C. The effects of limited thermal cycling under the extended test temperature, which ranged from -194 C to +150 C, on the operation of this chip as well as restart capability at the extreme cryogenic and hot temperatures were also investigated. The driver circuit was able to maintain good operation throughout the entire test regime between -194 C and +150 C without undergoing any major changes in its outputs signals and characteristics. The limited thermal cycling performed on the device also had no effect on its performance, and the driver chip was able to successfully restart at each of the extreme temperatures of -194 C and +150 C. The plastic packaging of this device was also not affected by either the short extreme temperature exposure or the limited thermal cycling. These preliminary results indicate that this new commercial-off-the-shelf (COTS) halfbridge eGaN FET driver integrated circuit has the potential for use in space exploration missions under extreme temperature environments. Further testing is planned under long-term cycling to assess the reliability of these parts and to determine their suitability for extended use in the harsh environments of space.
Micro Electro Mechanical Systems (MEMS) have been heralded for their ability to provide tremendous advantages in electronic systems through increased electrical performance, reduced power consumption, and higher levels of device integration with a reduction of board real estate. RF MEMS switch technology offers advantages such as low insertion loss (0.1- 0.5 dB), wide bandwidth (1 GHz-100 GHz), and compatibility with many different process technologies (quartz, high resistivity Si, GaAs) which can replace the use of traditional electronic switches, such as GaAs FETS and PIN Diodes, in microwave systems for low signal power (x < 500 mW) applications. Although the electrical characteristics of RF MEMS switches far surpass any existing technologies, the unknown reliability, due to the lack of information concerning failure modes and mechanisms inherent to MEMS devices, create an obstacle to insertion of MEMS technology into high reliability applications. All MEMS devices are sensitive to moisture and contaminants, issues easily resolved by hermetic or near-hermetic packaging. Two well-known failure modes of RF MEMS switches are charging in the dielectric layer of capacitive membrane switches and contact interface stiction of metal-metal switches. Determining the integrity of MEMS devices when subjected to the shock, vibration, temperature extremes, and radiation of the space environment is necessary to facilitate integration into space systems. This paper will explore the effects of different environmental stresses, operational life cycling, temperature, mechanical shock, and vibration on the first commercially available RF MEMS switches to identify relevant failure modes and mechanisms inherent to these device and packaging schemes for space applications. This paper will also describe RF MEMS Switch technology under development at NASA GSFC.
Previous testing of the Enhanced Power Conversion (EPC) eGaN FETs showed sensitivity to destructive single-event effects (SEE) effects to heavy ions. The presence of tungsten plugs in the gate area raises concerns that the device may be vulnerable to SEE from protons. Irradiation of biased and unbiased devices with heavy ion has results in some damage suspected of being due to total non-ionizing dose (TNID). Proton irradiation is a better radiation type to study this effect. This study presents the results of testing device with protons for SEE and TNID. No SEE in the EPC2012 device, the most sensitive device to SEE, were seen with 53 MeV protons at several angles. The devices continued to function after 1.5 Mrad (Si) of proton dose with only a slight shift in parameters. These results suggest that gross TNID will not be a factor in using these devices nor suffer from SEE due to protons. However, the device should be tested at with 500 MeV protons to guarantee to immunity proton SEE.