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Azimuth correlator circuit synthetic-aperature radar (SAR) is designed for single integrated circuit (IC) chip. Azimuth correlator modules constructed with sets of such chips could make real-time signal processing possible. Primary advantages are realized in areas of weight and power requirement reductions.
A description is presented of the fabrication of a new InSb CCD chip based on an improved process which eliminates the limitations inherent with the earlier techniques. This process includes planar junction formation and an aluminum and SiO2 material system which is amenable to state-of-the-art chemical and plasma delineation techniques. Further, the new chip integrates for the first time in monolithic format InSb IR detectors with an InSb CCD. The reported experiments represent the first operation of an InSb infrared CCD array. In addition to fuller characterization of the 20-element charge-coupled infrared imaging device, several factors which influence device performance are currently being addressed. These include surface state density, the CCD output circuit, and storage time (dark current).
This paper describes the application of a single-chip microcomputer in a high-altitude balloon instrumentation system. The system, consisting of a magnetometer, a stepping motor, a microcomputer and a gray code shaft encoder, is used to provide an orientation reference to point a scientific instrument at an object in space. The single-chip microcomputer, Intel's 8748, consisting of a CPU, program memory, data memory and I/O ports, is used to control the orientation of the system.
A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.
A number of studies have been conducted with the aim to apply parallel computation to problems associated with solving finite element equations arising in structural mechanics and fluid dynamics. These studies have provided many important results. The present investigation is concerned with a set of experiments designed to test two ideas, including configurability and substructuring. The considered algorithms and tests are intended for implementation on the Configurable, Highly Parallel (CHiP) family of architecture described by Snyder (1982). The ChiP computer is composed of homogeneous processing elements (PEs) placed at regular intervals in a lattice of programmable switches. Two examples of the role of configurability and substructuring for simple iterative algorithms are considered, giving attention to conjugate gradient iterations, and tridiagonal systems of equations.
Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.
Integrated circuit technology has been successfully applied to the design and fabrication of 0.5 x 0.5-cm planar multijunction solar-cell chips. Each of these solar cells consisted of six voltage-generating unit cells monolithically connected in series and fabricated on a 75-micron-thick, p-type, single crystal, silicon substrate. A contact photolithic process employing five photomask levels together with a standard microelectronics batch-processing technique were used to construct the solar-cell chip. The open-circuit voltage increased rapidly with increasing illumination up to 5 AM1 suns where it began to saturate at the sum of the individual unit-cell voltages at a maximum of 3.0 V. A short-circuit current density per unit cell of 240 mA/sq cm was observed at 10 AM1 suns.
A description of a working single chip implementation of a Reed-Solomon encoder. The code used is the Consultative Committee on Space Data Systems (CCSDS) standard (255,223) code. The architecture that leads to this single very large scale integration chip design makes use of a bit-serial finite field multiplication algorithm of E. R. Berlekamp.
One of the major problems in working at the geometry level for the generation of either test structure or functional circuit designs is the amount of labor involved in the design phase. To reduce the amount of labor involved in both the design and test of the structures used, JPL has developed a design and test program consisting of a Test Chip Assembler (TCA) and a Test Program Generator (TPG), which creates the geometrical description of the structures and generates the necessary test information using a high-level language. This system reduces the design time for a test chip by a factor of 30. To analyze the data obtained from wafer probing, a statistical package called STMJPL was developed. Some of the capabilities of the JPL software (STMJPL) are described.
A single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp.
The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.
Instrument errors made negligible. For each integration interval, both delay and rate of change of delay initialized to small fraction of chip - for example, to order of 10 to the negative 7th power - thereby making feedback control and extraction of delay highly accurate and flexible. With appropriate selection of sampling rate relative to chip rate, commensurability errors reduced to extremely small levels. In Global Positioning System (GPS) receiver, pseudorandom code sequence generated by simple digital logic incorporating effects of time, delay, and rate of change of delay. Flexibility in starting time and sum interval very useful in aligning correlation interval with beginnings and endings of data bits.
A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.
The authors describe an error-correction coding approach that allows operation in either burst or continuous modes at data rates of multiple hundreds of megabits per second. Bandspreading is low since the code rate is 7/8 or greater, which is consistent with high-rate link operation. The encoder, along with a hard-decision decoder, fits on a single application-specific integrated circuit (ASIC) chip. Soft-decision decoding is possible utilizing applique hardware in conjunction with the hard-decision decoder. Expected coding gain is a function of the application and is approximately 2.5 dB for hard-decision decoding at 10-5 bit-error rate with phase-shift-keying modulation and additive Gaussian white noise interference. The principal use envisioned for this technique is to achieve a modest amount of coding gain on high-data-rate, bandwidth-constrained channels. Data rates of up to 300 Mb/s can be accommodated by the codec chip. The major objective is burst-mode communications, where code words are composed of 32 n data bits followed by 32 overhead bits.
A novel RAM architecture supporting concurrent memory access and on-chip testing (CMAT) is proposed. A large-capacity memory chip is decomposed into test neighborhoods (TNDs), each of which is tested independently. When there are data stored in a TND, the data are saved into a buffer before testing the TND, and the TND's contents are restored using buffered data after testing the TND. If an external request is not made to the TND, the request can be directed to the addressed memory cells. Otherwise, the buffered data can be loaded back into the TND, or the request is detoured to a corresponding buffer. By deriving an analytical model, the performance penalty and hardware overhead of the CMAT architecture are shown to be very small.
Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human-like reasoning schemes which may include as little as six elemental behaviors embodied in fourteen qualitative rules.
This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.
Data from a MOSFET matrix on two JPL (CIT Jet Propulsion Laboratory) CRRES (Combined Release and Radiation Effects Satellite) chips, each behind different amounts of shielding, are presented. Space damage factors are nearly identical to ground test values for pMOSFETs. The results from neighboring rows of MOSFETs show similar radiation degradation. The SRD (Space Radiation Dosimeter) is used to measure the total dose accumulated by the JPL chips. A parameter extraction algorithm that does not underestimate threshold voltage shifts is used. Temperature effects are removed from the MOSFET data.