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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Destructive reverse bias pinning in perovskite/silicon tandem solar modules caused by perovskite hysteresis under dynamic shading

In this work, we demonstrate how perovskite hysteresis can result in permanent reductions in power output in perovskite/silicon tandem modules—including irreversible hotspot-induced damage—from only brief periods of shading. We show that reverse bias events in which a perovskite cell is biased above a threshold voltage—which in this work we find to be as low as –1.1 V—produces a temporary reduction in power output that is of sufficient magnitude to keep the cell pinned in reverse bias after the shading event ends. As a hysteretic phenomena, this crucial failure mode may be overlooked by static models of perovskite-based solar cells. Higher reverse bias voltages exacerbate the temporary reduction in short-circuit photocurrent, which is also sensitive to the level of illumination under reverse bias. Numerical device modelling demonstrates that this effect is consistent with our understanding of perovskite hysteresis as a consequence of mobile ion-electron coupling controlling rates of non-radiative recombination over time. Measurements of the dynamic response of single-junction perovskite cells are extrapolated to two-terminal and four-terminal perovskite/silicon tandem module modelling. We validate these models with measurements from an equivalent electronic circuit that represents a two-terminal perovskite–silicon tandem mini module. Two module-level solutions are discussed that address this issue, which includes increasing the number of bypass diodes and choosing better suited silicon bottom cells with higher shunter resistance in two-terminal tandem modules.

14 SOLAR ENERGY↗
DOE OSTI2020

Tri-gate GaN junction HEMT

This work presents a tri-gate GaN junction high-electron-mobility transistor (JHEMT) concept in which the p–n junction wraps around the AlGaN/GaN fins in the gate region. This tri-gate JHEMT differs from all existing GaN FinFETs and tri-gate HEMTs, as they employ a Schottky or a metal-insulator-semiconductor (MIS) gate stack. A tri-gate GaN JHEMT is fabricated using p-type NiO with the gate metal forming an Ohmic contact to NiO. The device shows minimal hysteresis and a subthreshold slope of 63 ± 2 mV/decade with an on-off current ratio of 10 8 . Compared to the tri-gate MISHEMTs fabricated on the same wafer, the tri-gate JHEMTs exhibit higher threshold voltage (V TH ) and achieve positive V TH without the need for additional AlGaN recess. In addition, this tri-gate JHEMT with a fin width of 60 nm achieves a breakdown voltage (BV) > 1500 V (defined at the drain current of 1 μA/mm at zero gate bias) and maintains the high BV with the fin length scaled down to 200 nm. In comparison, the tri-gate MISHEMTs with narrower and longer fins show punch-through at high voltages. Moreover, when compared to planar enhancement mode HEMTs, tri-gate JHEMTs show significantly lower channel sheet resistance in the gate region. Finally, these results illustrate a stronger channel depletion and electrostatic control in the junction tri-gate compared to the MIS tri-gate and suggest great promise of the tri-gate GaN JHEMTs for both high-voltage power and low-voltage power/digital applications.

36 MATERIALS SCIENCE↗
DOE OSTI2021

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) using plasma deposited BN as gate dielectric

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) were fabricated on Si substrates with a 10 nm boron nitride (BN) layer as a gate dielectric deposited by electron cyclotron resonance microwave plasma chemical vapor deposition. The material characterization of the BN/GaN interface was investigated by X-ray photoelectric spectroscopy (XPS) and UV photoelectron spectroscopy. The BN bandgap from the B1s XPS energy loss is ~5 eV consistent with sp2 bonding. The MISHEMTs exhibit a low off-state current of 1 × 10 –8 mA/mm, a high on/off current ratio of 10 9 , a threshold voltage of –2.76 V, a maximum transconductance of 32 mS/mm at a gate voltage of –2.1 V and a drain voltage of 1 V, a subthreshold swing of 69.1 mV/dec, and an on-resistance of 12.75 Ω·mm. The interface state density (D it ) is estimated to be less than 8.49 × 10 11 cm –2 eV –1 . Gate leakage current mechanisms were investigated by temperature-dependent current–voltage measurements from 300 K to 500 K. The maximum breakdown electric field is no less than 8.4 MV/cm. Poole–Frenkel emission and Fowler–Nordheim tunneling are indicated as the dominant mechanisms of the gate leakage through the BN gate dielectric at low and high electric fields, respectively.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Illumination-induced modulation of conductivity and Gunn oscillation properties in epitaxial GaAs

In this work, we illuminate a gallium arsenide (GaAs) Gunn device and study the light-induced changes of Gunn oscillation properties. We observe that illumination leads to the modulation of the Gunn threshold voltage, the Gunn oscillation magnitude, and the coherency of Gunn oscillation, with the nature of the modulation being closely related to the position of illumination on the device. These effects are attributed to the generation of optically excited carriers, which results in the modulation of conductivity and the electric field profile along the device. The finite element method is used to simulate the change of the field profile of the Gunn device caused by illumination. We also report an unexpected phenomenon of Gunn oscillation property manipulation with an optical chopper. In addition, wavelength-dependent, power-dependent, and pulsed illumination measurements are performed to help with further understanding the observations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

AlN/AlGaN/AlN quantum well channel HEMTs

We present a compositional dependence study of electrical characteristics of AlxGa1−xN quantum well channel-based AlN/AlGaN/AlN high electron mobility transistors (HEMTs) with x=0.25,0.44, and 0.58. This ultra-wide bandgap heterostructure is a candidate for next-generation radio frequency and power electronics. The use of selectively regrown n-type GaN Ohmic contacts results in contact resistance that increases as the Al content of the channel increases. The DC HEMT device characteristics reveal that the maximum drain current densities progressively reduce from 280 to 30 to 1.7 mA/mm for x=0.25,0.44, and 0.58, respectively. This is accompanied by a simultaneous decrease (in magnitude) in threshold voltage from −5.2 to −4.9 to −2.4 V for the three HEMTs. This systematic experimental study of the effects of Al composition x on the transistor characteristics provides valuable insights for engineering AlGaN channel HEMTs on AlN for extreme electronics at high voltages and high temperatures.

Physics↗
DOE OSTI2024

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

Here we report a comparative study of three rectifying gate metals, W, Pd, and Pt/Au, on ultrawide bandgap Al 0.86 Ga 0.14 N barrier/Al 0.7 Ga 0.3 N channel high electron mobility transistors for use in extreme temperatures. The transistors were electrically characterized from 30 to 600 °C in air. Of the three gate metals, the Pt/Au stack exhibited the smallest change in threshold voltage (0.15 V, or 9% change between the 30 and 600 °C values, and a maximum change of 42%), the highest on/off current ratio (1.5 × 10 6 ) at 600 °C, and a modest forward gate leakage current (0.39 mA/mm for a 3,V gate bias) at 600 °C. These favorable results showcase AlGaN channel high electron mobility transistors' ability to operate in extreme temperature environments.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Characterization of proton-induced damage in thick, p-channel skipper-CCDs

Here, in this work, we characterize the radiation-induced damage in two thick, p-channel skipper-CCDs irradiated unbiased and at room temperature with 217-MeV protons. We evaluate the overall performance of the sensors and demonstrate their single-electron/single-photon sensitivity after receiving a fluence on the order of 10 10 protons/cm 2 . Using the pocket-pumping technique, we quantify and characterize the proton-induced defects from displacement damage. We report an overall trap density of 0.134 traps/pixel for a displacement damage dose of 2.3 × 10 7 MeV/g. Three main proton-induced trap species were identified, V 2 , C i O i and V n O m , and their characteristic trap energies and cross sections were extracted. We found that while divacancies are the most common proton-induced defects, C i O i defects have a greater impact on charge integrity at typical operating temperatures because their emission-time constants are comparable or larger than typical readout times. To estimate ionization damage, we measure the characteristic output transistor curves. We found no threshold voltage shifts after irradiation. Our results highlight the potential of skipper-CCDs for applications requiring high-radiation tolerance and can be used to find the operating conditions in which effects of radiation-induced damage are mitigated.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Anisotropic Two-Dimensional Disordered Wigner Solid

The interplay between the Fermi sea anisotropy, electron-electron interaction, and localization phenomena can give rise to exotic many-body phases. An exciting example is an anisotropic two-dimensional (2D) Wigner solid (WS), where electrons form an ordered array with an anisotropic lattice structure. Such a state has eluded experiments up to now as its realization is extremely demanding: First, a WS entails very low densities where the Coulomb interaction dominates over the kinetic (Fermi) energy. Attaining such low densities while keeping the disorder low is very challenging. Second, the low-density requirement has to be fulfilled in a material that hosts an anisotropic Fermi sea. Here, we report transport measurements in a clean (low-disorder) 2D electron system with anisotropic effective mass and Fermi sea. The data reveal that at extremely low electron densities, when the r s parameter, the ratio of the Coulomb to the Fermi energy, exceeds ≃ 38, the current-voltage characteristics become strongly nonlinear at small dc biases. Several key features of the nonlinear characteristics, including their anisotropic voltage thresholds, are consistent with the formation of a disordered, anisotropic WS pinned by the ubiquitous disorder potential.

42 ENGINEERING↗
DOE OSTI2025

Securing 3D NAND Without Density Loss via In-Situ Encryption Using a Single Transistor XOR Cell

In this article, we push lightweight XOR-based in-situ encryption to extreme density by proposing a singletransistor XOR memory cell and applying it to 3D NAND, enabling secure data storage without density loss. Using a ferroelectric field-effect transistor (FeFET) as an example technology, we demonstrate that: i) a single-transistor memory can realize the XOR function by exploiting the ability to charge the source and drain separately and control current flow direction, eliminating the need for conventional encrypted cells that rely on complementary devices; ii) with a XOR-based cipher, encryption and decryption can be mapped to in-situ array operations, where ciphertext is stored as the threshold voltage (VTH) states of FeFETs in a NAND string, and decryption is achieved through read operations using key-dependent complementary source/drain bias; iii) the proposed technique is scalable to multi-level cell (MLC) storage by encrypting and decrypting data bit by bit; iv) using an integrated NAND FeFET array, we experimentally demonstrate encryption and decryption operations for both single-level cell (SLC) and MLC storage; v) systemlevel benchmarking shows that the proposed technique achieves 48× and 278× improvements in encryption and decryption throughput, respectively, compared to AES.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Operation of AlGaN Channel HEMTs at 850 °C With ON/OFF Ratio >10 4

Here, we report 850 ° C operation of ultrawide bandgap (UWBG) Al-rich Al 0.68 Ga 0.32 N channel high electron mobility transistors (HEMTs) at atmospheric pressure in nitrogen ambient. Temperature dependent DC electrical characteristics were measured in situ up to 850 ° C, after exposure to 850 ° C for 60 minutes, and at 25 ° C after high temperature testing. At 850 ° C (time, t = 0 min), all HEMTs tested maintained an on/off ratio greater than 10 4 (maximum of 4.6 × 10 4 ). The threshold voltage demonstrated excellent stability with less than ±10% deviation. After returning to 25 ° C, the devices showed negligible degradation. In fact, the off-state gate current decreased and on/off ratio slightly increased. The robustness of these UWBG AlGaN transistors at temperatures up to 850 ° C demonstrates their viability for extreme environment applications.

AlGaN↗
DOE OSTI2026

Temperature-Dependent Transport Characteristics of 2D MoS2 Channel FETs Grown Using Salt-Based Precursors

D Transition Metal Dichalcogenides (TMDs), particularly MoS2, are promising candidates for sub-10 nm Gate All Around (GAA) CMOS FETs. Salt-assisted Chemical Vapor Deposition (CVD) enable lateral MoS2 growth at atmospheric pressure and low temperatures. This work analyzes salt-based precursor-driven CVD-grown MoS2 FETs at various temperatures. MoS2 was grown using Ammonium Molybdate salt, sulfurized at 750∘C, and transferred onto p−Si3/SiO2 substrates. At room temperature, threshold voltage (VT) ranged from -35 V to -25 V, with a peak drain current of 1.2μA/μm. As temperature increased above 325K, VT shifted exponentially, and carrier mobility dropped significantly. At 400 K, the gate lost channel control, though gate leakage current remained low. These results are compared with non-salt-based MoS2 growth to assess salt precursor effects.Notice: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (https://www.energy.gov/doe-public-access-plan).

Jones, Andrew [ORNL] (ORCID:0009000233849687)↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
DOE OSTI2025

Interfacial oxide and other species in trimethylaluminum-pretreated atomic layer deposition-Al 2 O 3 /GaN characterized by sputter-assisted ToF-SIMS

Deposition techniques, like atomic layer deposition (ALD), are used to form high-quality dielectrics for GaN-based metal–oxide–semiconductor (MOS) gate structures due to the lack of a reliable thermal oxide in GaN. Moreover, interfacial GaO x from pre-existing native oxides is thought to adversely impact channel carrier dynamics and induce undesired threshold voltage shifts in GaN-based MOS gate structures. Exposure of the GaN surface to the trimethylaluminum (TMA) precursor prior to standard alumina ALD decreases the native oxide layer on GaN, but the extent of chemical modification has not been well studied in the context of interface composition in a MOS gate structure. Herein, we compare annealed 55 nm Al 2 O 3 dielectric films on GaN grown using either a water-first ALD process or a process including sequential pulses of TMA immediately before the initiation of Al 2 O 3 ALD. Time-of-Flight Secondary Ion Mass Spectrometry measures differences in the interfacial GaO x content between each ALD film. Here, it also detects surface contaminant species like Si, F, S, and C. Furthermore, we report the formation of an AlN species at the Al 2 O 3 /GaN interface, which is more prominent for the film grown using the TMA pre-pulse step. In general, this work demonstrates that the TMA pre-pulse step is an effective strategy for cleaning substrate surfaces prior to ALD.

Atomic layer deposition↗
DOE OSTI2025

On Rate-Limiting Mechanisms in NMC Cathodes: The Interplay of Low and High Current Constraints

In this study, we investigate the rate performance limits in LiNi 0.6 Mn 0.2 Co 0.2 O 2 cathodes for lithium-ion batteries, focusing on how cathode thickness, porosity, and threshold voltage impact discharge capacity. By conducting galvanostatic discharge experiments across a wide range of current densities using cathodes of varying thicknesses and porosities, we identify two distinct rate-limiting mechanisms: ionic liquid-diffusion and Ohmic/charge-transfer limitations. Our findings show that thick, dense cathodes are primarily limited by lithium diffusion in the electrolyte, while thinner and more porous cathodes are dominated by Ohmic/charge-transfer limitations, particularly at higher lower cutoff voltages. Crucially, these results allow us to identify the rate-limiting mechanisms in different cathode configurations, offering clear insights into how cathode design can be optimized for improved performance. Understanding these mechanisms is essential for designing next-generation batteries with enhanced rate performance, which is critical for applications such as electric vehicles and renewable energy storage systems.

Brischetto, Martin (ORCID:0000000339865813)↗
DOE OSTI2024

Electron Density Measurements Using USPR (Final Scientific/Technical Report)

UC Davis has fabricated an ultrashort pulse reflectometer (USPR) diagnostic instrument for electron density profile measurements on compact, short duration, magnetically-confined fusion-energy concept devices such as spheromaks and FRCs. The USPR system transmits extremely short duration (~few nsec) chirped waveforms that together span 29 to 75 GHz. These chirped waveforms illuminate and reflect from the target plasma, with each frequency component reflecting from a different density layer (higher frequencies probe deeper into the plasma before reflecting). The reflected waveforms are split into roughly 42 different frequencies; time-of-flight (TOF) measurements made at each frequency with high resolution (~25 psec measurement resolution which corresponds to ~5 mm). These TOF data may then be inverted via software to generate electron density profiles with high time resolution (~10 μsec). At the heart of the system is a field programmable gate array (FPGA) based controller which collects and processes all of the USPR data in addition to generating all of the control signals required for maximum flexibility. The FPGA controller has the software flexibility to be easily reconfigured for different plasma devices, and the entire system sufficiently compact to be easily and quickly transported between devices. A high speed impulse generator was transformed into a set of three ultrashort pulse transmitter chirps using a combination of dispersive waveguide, frequency doublers and high-pass filters. A mm-wave controller was fabricated to sequentially switch between the three chirps, directing the chirps one-by-one to three different mm-wave assemblies spanning 29-75 GHz. Each mm-wave assembly consists of a high power active multiplier chain which converts the transmitter chirp to higher frequencies, and a broadband mixer which downconverts the reflected waveform to the 2-18 GHz range of the UPSR receiver. The 16-channel receiver (shared by all 3 mm-wave assemblies) was fabricated employing custom TOF modules capable of operating at a high 1 MHz sampling rate. Laboratory testing of the full system revealed the presence of unwanted harmonics from the multiplication process, with interference observed in the downconverted reflections at selected frequency channels that could not be completely filtered out. Additional interference effects arising from internal reflections within the mm-wave assemblies were minimized using a high-speed switch which served to “gate out” much of these reflections. The USPR diagnostic was transported and installed onto the HIT-SIU plasma device, becoming operational on 11/08/2022. Although designed to span 3 distinct mm-wave bands, the HIT-SIU plasmas at this time were sufficiently low density such that only the lowest of the three bands was likely to have strong plasma reflections. The system was then set to operate on only the lowest band (assembly #1), with data collected every 1 μsec rather than 3 μsec which would have been the case when cycling through all three bands. Connected to HIT-SIU, time-varying plasma reflections were observed on 9 of 16 possible frequency channels. Close examination of the data collected revealed issues previously unobserved in laboratory testing, associated with (a) reflections from the small aperture horns required for operation within the HIT-SIU device, and (b) a dependence of the recorded TOF with the threshold voltage of a given channel. Plans were made to address each of these issues before undertaking any future campaigns.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

CMS HGCAL ECON-D ASIC : Impact of CMOS fabrication process tuning on performance and radiation tolerance

The CMS experiment’s High Granularity Calorimeter (HGCAL) upgrade will replace CMS’s existing endcap calorimeters in preparation for the High Luminosity LHC. To effectively use over 6 million channels of this “imaging”calorimeter, CMS has developed two novel Endcap Concentrator (ECON) ASICs to perform data compression/selection on detector. The ECON-D ASIC operates on the 750kHz data path, and the ECON-T ASIC on the 40MHz trigger path. These 65 nm CMOS ASICs are radiation tolerant to 200 Mrad and low power, operating at less than 2.5 mW/channel. The first full-functionality prototype ECONs were produced and characterized in 2021-23, and an initial engineering run was performed in 2024. ECON-D radiation testing for the engineering run revealed that the chip’s internal SRAMs produce intermittent read errors for a non-negligible fraction of chips. Further investigation indicated that the SRAM performance is highly sensitive to the exact parameters of the CMOS fabrication process. To both study this process sensitivity and mitigate SRAM performance issues, twenty ECON wafers were produced in 2025 with a range of doping concentrations designed to tune the underlying transistor threshold voltage by 0%, 5%, 10%, and 15% from nominal. This talk will present first measurements of ECON-D performance, power consumption, and radiation tolerance for these four variations of CMOS process.

Syal, Chinar [Fermilab]↗
DOE OSTI2026

Learned adaptive properties for mitigation of weight perturbations in embedded spiking networks

Recent years have seen an increased importance of neural network inference in edge-based scenarios, which impose size and power constraints requiring novel computing devices. These same edge scenarios may require operating over long periods of time, or exposure to extreme environments, resulting in a drift of neural network weights that cause degraded performance. In searching for ways to develop neural network approaches that perform robustly under these conditions, we propose a biologically-inspired mechanism for the dynamic adaptation of within-neuron parameters that is guided by a global context signal carrying information about perturbations and variability in incoming stimuli. Specifically, we demonstrate that adaptive voltage thresholds or neuronal time constants, when informed by a global context signal, can enable network-level mechanisms to recover from perturbed synaptic weights. Consistent with prior literature, the context-modulated approach is effective for recurrent, but not feedforward networks, by modulating network level dynamics. We demonstrate this approach successfully recovers performance in image classification tasks and spatiotemporal tracking tasks under idealized and Gaussian noise as well as for realistic perturbations from a memristive device when exposed to ionizing radiation. Finally, we discuss how this approach enables the design of robust and energy-efficient neuromorphic systems that perform well, even in resource-constrained scenarios with extreme environments such as edge processing.

context modulation↗
DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗