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At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

DOE OSTI2024

Selective solid-state isolation of NMR circuit elements using back-to-back field effect transistors

Nuclear Magnetic Resonance (NMR) electronics that employ selective solid-state isolation of circuit elements can include solid-state switches, such as back-to-back Field Effect Transistor (FET) pairs, and isolated gate drive electronics adapted to operate the solid-state switches in order to selectively decouple induction coils from receive electronics. The solid-state switches can be placed in series to achieve higher standoff voltages, and can be configured for low on resistance and short switching times. The gate drive electronics can include electrical isolation components adapted to enhance standoff voltages and reduce electrical noise at the selectively isolated receive electronics.

Walsh, David O.↗

DOE OSTI2024

Multi-amplifier Sensing Charge-coupled Devices for Next Generation Spectroscopy

We present characterization results and performance of a prototype Multiple-Amplifier Sensing (MAS) silicon charge-coupled device (CCD) sensor with 16 channels potentially suitable for faint object astronomical spectroscopy and low-signal, photon-limited imaging. The MAS CCD is designed to reach sub-electron readout noise by repeatedly measuring charge through a line of amplifiers during the serial transfer shifts. Using synchronized readout electronics based on the Dark Energy Spectroscopic Instrument CCD controller, we report a read noise of 1.03 e$^{−}$ rms pix$^{−1}$ at a speed of 26 μs pix$^{−1}$ with a single-sample readout scheme where charge in a pixel is measured only once for each output stage. At these operating parameters, we find the amplifier-to-amplifier charge transfer efficiency (ACTE) to be >0.9995 at low counts for all amplifiers but one for which the ACTE is 0.997. This charge transfer efficiency falls above 50,000 electrons for the read-noise optimized voltage configuration we chose for the serial clocks and gates. The amplifier linearity across a broad dynamic range from ∼300 to 35,000 e$^{−}$ was also measured to be ±2.5%. We describe key operating parameters to optimize on these characteristics and describe the specific applications for which the MAS CCD may be a suitable detector candidate.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2025

Mechanisms enabling reconfigurability and long-term retention in vanadium oxide electrochemical memory

Phase coexistence in nanoscale electrochemical random-access memory (ECRAM) has recently been demonstrated to enable both information storage and extraordinary reconfigurability. These proof-of-principle demonstrations have left the mechanistic details of such a process unresolved. Particularly, the mechanisms that stabilize the multiple phases, and the underlying processes behind sustained memory retention, remain unclear, and are necessary to design such devices. Here we report microscale ECRAM devices composed of V⁢O𝑥, which enables us to directly probe the active region in an operando fashion using optical techniques. Using Raman mapping, we show the phase coexistence driven by the electrochemical injection of O vacancies to be spatially uniform (i.e., with no filaments). The stability was observed to be unusually long, with 1% loss over 14 years in ambient conditions. First-principles calculations of the oxygen vacancy formation energies in V⁢O 𝑥 further support the thermodynamic coexistence of multiple V⁢O 𝑥 phases and clarify the origin of the observed long-term retention in the ECRAM devices. Further, we demonstrate single devices that can be voltage programmed to exhibit synaptic, neuronal, and reconfigurable logic gate functionalities. Furthermore, we not only uncover the phase coexistence mechanism that may help device design, but also demonstrate the circuit-level applications of reconfigurability.

Electrical conductivity↗

DOE OSTI2025

Enhancement-Mode GaN Monolithic Bidirectional Switch With Breakdown Voltage Over 3.3 kV

Here, this work demonstrates a GaN enhancement-mode monolithic bidirectional switch (MBDS) with breakdown voltage (BV) higher than 3.3 kV in both polarities. This MBDS is realized on a dual p-GaN gate high electron mobility transistor (HEMT) platform on sapphire substrate. It features a novel dual junction termination extension design for electric field management, which is built on the p-GaN layer in the gate stack and does not require epitaxial regrowth. The GaN MBDS exhibits symmetric on-state characteristics in both directions with a threshold voltage (V th ) of 0.6 V and a low specific on-resistance (R on,sp ) of 5.6 m Ω · cm2. This device presents the highest BV, as well as one of the best BV and R on,sp trade-offs, in all the reported MBDS devices. The R on,sp is lower than the performance limit of conventional BDS realized by two discrete devices. This 3.3 kV GaN MBDS opens the door for developing new circuit topologies and advancing system performance in medium-voltage power electronics.

42 ENGINEERING↗

DOE OSTI2024

Study of graphene p-n junctions formed by the electrostatic modification of the SiO2 substrate

Abstract We study the transport properties of mm-scale CVD graphene p-n junctions, which are formed in a single gated graphene field effect transistor configuration. Here, an electrical-stressing-voltage technique served to modify the electrostatic potential in the SiO 2 /Si substrate and create the p-n junction. We examine the transport characteristics about the Dirac points that are localized in the perturbed and unperturbed regions in the graphene channel and note the quantitative differences in the Hall effect between the perturbed and unperturbed regions. The results also show that the longitudinal resistance is highly sensitive to the external magnetic field when the Hall bar device operates as a p-n junction.

Science & Technology - Other Topics↗

DOE OSTI2025

Photoconductive Semiconductor Switches: Materials, Physics, and Applications

Photoconductive semiconductor switching (PCSS) devices have unique characteristics to address the growing need for electrically isolated, optically gated, picosecond-scale jitter devices capable of operating at high voltage, current, and frequency. The state of the art in material selection, doping, triggering, and system integration in PCSSs is presented. The material properties and doping considerations of GaN, GaAs, SiC, diamond, and β-Ga2O3 in the fabrication of PCSS devices are discussed. A review of the current understanding of the physics of the high-gain mode known as lock-on is presented.

36 MATERIALS SCIENCE↗

DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗

DOE OSTI2024

Tuning Exciton Emission via Ferroelectric Polarization at a Heterogeneous Interface between a Monolayer Transition Metal Dichalcogenide and a Perovskite Oxide Membrane

Here we demonstrate the integration of a thin BaTiO 3 (BTO) membrane with monolayer MoSe 2 in a dual gate device that enables in-situ manipulation of the BTO ferroelectric polarization with a voltage pulse. While two-dimensional (2D) transition metal dichalcogenides (TMDs) offer remarkable adaptability, their hybrid integration with other families of functional materials beyond the realm of 2D materials has been challenging. Released functional oxide membranes offer a solution for 2D/3D integration via stacking. 2D TMD excitons can serve as a local probe of the ferroelectric polarization in BTO at a heterogeneous interface. Using photoluminescence (PL) of MoSe 2 excitons to optically readout the doping level, we find that the relative population of charge carriers in MoSe 2 depends sensitively on the ferroelectric polarization. This finding points to a promising avenue for future-generations versatile sensing devices with high sensitivity, fast read-out, and diverse applicability for advanced signal processing.

42 ENGINEERING↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2026

MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator

We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.

36 MATERIALS SCIENCE↗

DOE OSTI2026

Temperature-Dependent Transport Characteristics of 2D MoS2 Channel FETs Grown Using Salt-Based Precursors

D Transition Metal Dichalcogenides (TMDs), particularly MoS2, are promising candidates for sub-10 nm Gate All Around (GAA) CMOS FETs. Salt-assisted Chemical Vapor Deposition (CVD) enable lateral MoS2 growth at atmospheric pressure and low temperatures. This work analyzes salt-based precursor-driven CVD-grown MoS2 FETs at various temperatures. MoS2 was grown using Ammonium Molybdate salt, sulfurized at 750∘C, and transferred onto p−Si3/SiO2 substrates. At room temperature, threshold voltage (VT) ranged from -35 V to -25 V, with a peak drain current of 1.2μA/μm. As temperature increased above 325K, VT shifted exponentially, and carrier mobility dropped significantly. At 400 K, the gate lost channel control, though gate leakage current remained low. These results are compared with non-salt-based MoS2 growth to assess salt precursor effects.Notice: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (https://www.energy.gov/doe-public-access-plan).

Jones, Andrew [ORNL] (ORCID:0009000233849687)↗

DOE OSTI2026

Heterogeneous Integration of Flipped Oxide Heterostructure Membranes for Nanoelectronics

Freestanding complex oxide membranes enable the release and transfer of epitaxial films, offering new design freedoms for next‐generation electronics. While the LaAlO 3 /SrTiO 3 (LAO/STO) heterostructure exhibits remarkable tunable conductivity at its interface, the active interface remains buried beneath the substrate, limiting access to this functionality. Here, we demonstrate how the LAO/STO heterostructure, in membrane form, can be flipped and precisely positioned on silicon and other platforms using polymer‐free micromanipulation. The transferred membranes preserve atomically smooth surfaces, high crystallinity, and key electronic properties. Through the 44‐nm insulating STO layer, ultra‐low‐voltage electron‐beam lithography (ULV‐EBL) writes conductive nanostructures at the now‐accessible STO/LAO interface, offering the potential to function as programmable local gates that modulate charge carriers in the underlying silicon. The platform establishes a general strategy for integrating complex oxide heterostructures with semiconductors, quantum materials, and flexible substrates, enabling new architectures for reprogrammable nanoelectronic devices.

36 MATERIALS SCIENCE↗

DOE OSTI2025

Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level

Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.

Dual-metal gate work functions↗

DOE OSTI2025

Operation of AlGaN Channel HEMTs at 850 °C With ON/OFF Ratio >10 4

Here, we report 850 ° C operation of ultrawide bandgap (UWBG) Al-rich Al 0.68 Ga 0.32 N channel high electron mobility transistors (HEMTs) at atmospheric pressure in nitrogen ambient. Temperature dependent DC electrical characteristics were measured in situ up to 850 ° C, after exposure to 850 ° C for 60 minutes, and at 25 ° C after high temperature testing. At 850 ° C (time, t = 0 min), all HEMTs tested maintained an on/off ratio greater than 10 4 (maximum of 4.6 × 10 4 ). The threshold voltage demonstrated excellent stability with less than ±10% deviation. After returning to 25 ° C, the devices showed negligible degradation. In fact, the off-state gate current decreased and on/off ratio slightly increased. The robustness of these UWBG AlGaN transistors at temperatures up to 850 ° C demonstrates their viability for extreme environment applications.

AlGaN↗

DOE OSTI2025

Extreme Enhancement-Mode Operation Accumulation Channel Hydrogen-Terminated Diamond FETs with V th < -6 V and High on-Current

In this work, a new Field Effect Transistor device concept based on hydrogen-terminated diamond (H-diamond) is demonstrated that operates in an Accumulation Channel rather than a Transfer Doping regime. The FET devices demonstrate both extreme enhancement-mode operation and high on-current with improved channel charge mobility compared to Transfer-Doped equivalents. Electron-beam evaporated Al 2 O 3 is used on H-diamond to suppress the Transfer Doping mechanism and produce an extremely high ungated channel resistance. A high-quality H-diamond surface with an unpinned Fermi level is crucially achieved, allowing for the formation of a high-density hole accumulation layer by gating the entire device channel which is encapsulated in dual-stacks of Al 2 O 3 . Completed devices with gate/channel length of 1 µm demonstrate record threshold voltage < -6 V with on-current > 80 mA mm -1 . Carrier density and mobility figures extracted by CV analysis indicate a high 2D charge density of ≈ 2 × 10 12 cm -2 and increased hole mobility of 110 cm 2 V -1 s -1 in comparison with more traditional Transfer-Doped H-diamond FETs. These results demonstrate the most negative threshold voltage yet reported for H-diamond FETs and highlight a powerful new strategy to greatly improve carrier mobility and enable enhanced high power and high frequency diamond transistor performance.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2024

A Low-Profile Gate Power Supply for a SiC Phase Leg with Reduced Isolation Capacitance

Gate driver power supply (GDPS) for SiC devices needs power to 5 W as the switching frequency increases to hundreds of kHz. Resonant converters with planar magnetics demand GDPS with a lower profile. Also, the isolation capacitance (Cp) needs to be minimized for SiC devices with high dv/dt. This paper proposed a planar 5 W*2, 20 V isolated gate power supply for a SiC phase leg in the EV traction inverter. Air-core magnetics with PCB windings are applied for low profile. A single-switch resonant Class-E topology is proposed with zero-voltage switching at 6.78 MHz to minimize the magnetics footprint for a 6 pF Cp. Compared with commercial power supplies with similar power, the proposed power supply reduced the profile and Cp by more than half without sacrificing its efficiency and power density.

Li, Bo↗