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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Hoenk, Michael E.↗
DOE OSTI2024

Stacked-Die SiC Half-Bridge Module with Minimum Loop Inductance

Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.

Ribeiro, Pedro↗
NASA NTRS2012

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, TImothy M.↗
NASA NTRS2012

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, Timothy M.↗
NASA NTRS2012

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, Timothy M.↗
NASA NTRS2012

Enabling Large Focal Plane Arrays through Mosaic Hybridization

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Miller, Timothy M.↗
NASA NTRS2011

Performance Comparison of Wireless Sensor Network Standard Protocols in an Aerospace Environment: ISA100.11a and ZigBee

Wireless Sensor Networks (WSNs) can provide a substantial benefit in spacecraft systems, reducing launch weight and providing unprecedented flexibility by allowing instrumentation capabilities to grow and change over time. Achieving data transport reliability on par with that of wired systems, however, can prove extremely challenging in practice. Fortunately, much progress has been made in developing standard WSN radio protocols for applications from non-critical home automation to mission-critical industrial process control. The relative performances of candidate protocols must be compared in representative aerospace environments, however, to determine their suitability for spaceflight applications. In this paper, we will present the results of a rigorous laboratory analysis of the performance of two standards-based, low power, low data rate WSN protocols: ZigBee Pro and ISA100.11a. Both are based on IEEE 802.15.4 and augment that standard's specifications to build complete, multi-hop networking stacks. ZigBee Pro targets primarily the home and office automation markets, providing an ad-hoc protocol that is computationally lightweight and easy to implement in inexpensive system-on-a-chip components. As a result of this simplicity, however, ZigBee Pro can be susceptible to radio frequency (RF) interference. ISA100.11a, on the other hand, targets the industrial process control market, providing a robust, centrally-managed protocol capable of tolerating a significant amount of RF interference. To achieve these gains, a coordinated channel hopping mechanism is employed, which entails a greater computational complexity than ZigBee and requires more sophisticated and costly hardware. To guide future aerospace deployments, we must understand how well these standards relatively perform in analog environments under expected operating conditions. Specifically, we are interested in evaluating goodput -- application level throughput -- in a representative crewed environment in the presence of varying levels of 802.11g Wi-Fi traffic. To do so, we use the NASA Johnson Space Center Wireless Habitat Testbed (WHT), a metallic, habitation-sized module designed for co-existence testing of wireless systems. In its quiescent state, the sealed WHT provides an RF-quiet environment to which we can selectively add interfering systems; it also provides a realistic level of multi-path self-interference for systems under investigation. In our test, we deploy two representative five node networks, configured in a star topology with all nodes reporting directly to a WSN gateway. Each ZigBee network WSN node is built using a Texas Instruments (TI) CC2530 system-on-a-chip radio running TI's ZigBee Pro Z-stack. Each ISA100.11a network node is built using a Nivis VersaNode 210 system-on-a-chip radio. In both cases, radios interface with TI MSP430-F5438 microcontroller implementing a common test application. Interference is provided by a D-link 802.11g Wi-Fi router transporting traffic generated using the Iperf network testing tool. For the single-channel ZigBee network, effects of both direct and indirect Wi-Fi interference are evaluated. For the channel-hopping ISA100.11a network, effects of interference from multiple Wi-Fi routers configured in non-overlapping 802.11g channels are evaluated. Our results show that, in general, the more lightweight ZigBee network performs well at low interference levels, but performance degrades as interference increases. Conversely, the more complex and costly ISA100.11a network continues to perform well as Wi-Fi interference levels increase.

Wagner, Raymond S.↗
NASA NTRS2013

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile↗
NASA NTRS1994

Three-Dimensional Vertical-Bloch-Line Memory System

In proposed magnetic memory system without moving parts, data is stored in stack of two-dimensional vertical-Bloch-line (VBL) memory chips or modules. System similar to one described in "Three-Dimensional Magnetic-Bubble Memory System" (NPO-18533). Each VBL module in this memory system silimar to module described in "Vertical-Bloch-Line Memory" (NPO-18467). Advantages include high storage density, high speed, nonvolatility, and insensitivity to ionizing radiation.

Katti, Romney R.↗
DOE OSTI2026

A Cryogenic Muon Tagging System Integrated with a Superconducting Qubit Device for Radiation-Induced Error Mitigation

Superconducting qubits are highly sensitive to ionizing radiation, which can induce correlated errors and limit scalable fault-tolerant quantum computing. In particular, cosmic-ray muons can deposit energy in the substrate, generating phonon bursts that break Cooper pairs and produce quasiparticles, leading to correlated decoherence events across multiple qubits. We present the development of a cryogenic muon tagging system based on Kinetic Inductance Detectors (KIDs) and its integration with superconducting quantum hardware. Originally developed within the ACE-SuperQ project and validated as a standalone detector, the system demonstrated a muon tagging efficiency of approximately 90% and excellent agreement with Monte Carlo simulations. Building on this validation, the tagging system has been integrated with a multi-qubit superconducting chip operated in a dilution refrigerator. The detector configuration consists of a multi-layer KID stack arranged above and below the quantum device, enabling time-coincident identification of muon-induced events within the same cryogenic environment. The integrated setup has been successfully commissioned, enabling simultaneous operation of the qubit chip and the muon tagging system. A first measurement campaign has been carried out, and preliminary data show time-correlated events between the muon tagging detectors and the qubit readout. A quantitative analysis of radiation-induced effects on qubit performance is currently ongoing. This work represents a step toward the implementation of event-level radiation tagging as a tool for characterizing and potentially mitigating correlated errors in superconducting quantum processors, while establishing a modular platform for future studies at the interface between particle physics and quantum information science.

Roy, Tanay [Fermilab] (ORCID:000000019442862X)↗
NASA NTRS1996

(abstract) A High Throughput 3-D Inner Product Processor

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

imaging parallel processing algorithms linear vect↗
DOE OSTI2023

Deployment of ADTimePix3 areaDetector Driver at Neutron and X-ray User Facilities

TimePix3 is a 65k hybrid pixel readout chip with simultaneous Time-of-Arrival (ToA) and Time-over-Threshold (ToT) recording in each pixel*. The chip operates without a trigger signal with a sparse readout where only pixels containing events are read out. The flexible architecture allows 40 MHits/s/cm² readout throughput, using simultaneous readout and acquisition by sharing readout logic with transport logic of superpixel matrix formed using 2x4 structure. The chip ToA records 1.5625 ns time resolution. The X-ray and charged particle events are counted directly. However, indirect neutron counts use 6Li fission in a scintillator matrix, such as ZnS(Ag). The fission space-charge region is limited to 5-9 um. A photon from scintillator material excites a photocathode electron, which is further multiplied in dual-stack MCP. The neutron count event is a cluster of electron events at the chip. We report on the EPICS areaDetector** ADTimePix3 driver that controls Serval*** using json commands. The driver directs data to storage and to a real-time processing pipeline and configures the chip. The time-stamped data are stored in raw .tpx3 file format and passed through a socket where the clustering software identifies individual neutron events. The conventional 2D images are available as images for each exposure frame, and a preview is useful for sample alignment. The areaDetector driver allows integration of time-enhanced capabilities of this detector into SNS beamlines controls and unprecedented time resolution.

Gofron, Kaz↗
DOE OSTI2021

The upgrade of the ALICE TPC with GEMs and continuous readout

The upgrade of the ALICE TPC will allow the experiment to cope with the high interaction rates foreseen for the forthcoming Run 3 and Run 4 at the CERN LHC. In this article, we describe the design of new readout chambers and front-end electronics, which are driven by the goals of the experiment. Gas Electron Multiplier (GEM) detectors arranged in stacks containing four GEMs each, and continuous readout electronics based on the SAMPA chip, an ALICE development, are replacing the previous elements. The construction of these new elements, together with their associated quality control procedures, is explained in detail. Finally, the readout chamber and front-end electronics cards replacement, together with the commissioning of the detector prior to installation in the experimental cavern, are presented. After a nine-year period of R&D, construction, and assembly, the upgrade of the TPC was completed in 2020.

47 OTHER INSTRUMENTATION↗
NASA NTRS2015

High Frequency Design Considerations for the Large Detector Number and Small Form Factor Dual Electron Spectrometer of the Fast Plasma Investigation on NASA's Magnetospheric Multiscale Mission

Each half of the Dual Electron Spectrometer (DES) of the Fast Plasma Investigation (FPI) on NASA's Magnetospheric MultiScale (MMS) mission utilizes a microchannel plate Chevron stack feeding 16 separate detection channels each with a dedicated anode and amplifier/discriminator chip. The desire to detect events on a single channel with a temporal spacing of 100 ns and a fixed dead-time drove our decision to use an amplifier/discriminator with a very fast (GHz class) front end. Since the inherent frequency response of each pulse in the output of the DES microchannel plate system also has frequency components above a GHz, this produced a number of design constraints not normally expected in electronic systems operating at peak speeds of 10 MHz. Additional constraints are imposed by the geometry of the instrument requiring all 16 channels along with each anode and amplifier/discriminator to be packaged in a relatively small space. We developed an electrical model for board level interactions between the detector channels to allow us to design a board topology which gave us the best detection sensitivity and lowest channel to channel crosstalk. The amplifier/discriminator output was designed to prevent the outputs from one channel from producing triggers on the inputs of other channels. A number of Radio Frequency design techniques were then applied to prevent signals from other subsystems (e.g. the high voltage power supply, command and data handling board, and Ultraviolet stimulation for the MCP) from generating false events. These techniques enabled us to operate the board at its highest sensitivity when operated in isolation and at very high sensitivity when placed into the overall system.

Microchannel plates high frequency performance↗
DOE OSTI2022

Advanced Heterogeneous Integration Enabled by 3D Freestanding Membranes—From Material Growths to Applications

For the future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, the need for flexibility and stackability of electronic products has substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically compliant and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. Such performance-mechanical compliance dilemma could be resolved by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. Such dream electronic systems could be realized by producing single-crystalline freestanding membranes. For the past few decades, various layer transfer techniques (a.k.a layer liftoff techniques) have been developed to produce single-crystalline freestanding membranes. In today's talk, I will present the survey of the layer liftoff techniques and go over how these strategies unlock new ways of manufacturing advanced electronic systems. In addition, I will introduce unprecedented artificial heterostructure devices enabled by stacking of those freestanding 3D material membranes, e.g., the world's smallest vertically-stacked full-color micro-LEDs, the world's best multiferroic devices, chip-less wireless e-skin, and reconfigurable hetero-integrated chips with AI accelerators.

Kim, Jeehwan↗
DOE OSTI2022

Advanced Heterogeneous Integration Enabled by 3D Freestanding Membranes—From Material Growths to Applications

For the future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, the need for flexibility and stackability of electronic products has substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically compliant and less costly than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-crystalline inorganic materials. Such performance-mechanical compliance dilemma could be resolved by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. Such dream electronic systems could be realized by producing single-crystalline freestanding membranes. For the past few decades, various layer transfer techniques (a.k.a layer liftoff techniques) have been developed to produce single-crystalline freestanding membranes. In today's talk, I will present the survey of the layer liftoff techniques and go over how these strategies unlock new ways of manufacturing advanced electronic systems. In addition, I will introduce unprecedented artificial heterostructure devices enabled by stacking of those freestanding 3D material membranes, e.g., the world's smallest vertically-stacked full-color micro-LEDs, the world's best multiferroic devices, chip-less wireless e-skin, and reconfigurable hetero-integrated chips with AI accelerators.

Kim, Jeehwan↗