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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Three influential factors on colloidal nanoparticle deposition for heat conduction enhancement in 3D chip stacks

Thermal management is one of the major challenges facing the development of three-dimensional (3D) chip stacks. Recently, experimental studies have shown that neck-based thermal structure (NTS) between chip layers formed by drying of colloidal suspension in cavity filled with micro-size particles can improve the vertical heat conduction threefold. However, a deep understanding of the mechanisms of neck formation and its influence on heat conduction is still lacking. In this paper, we numerically study the effects of three parameters, i.e., initial nanoparticle concentration, drying temperature and chip surface wettability on neck formation between filler particles and on the resulting heat conduction of the NTS. With increasing nanoparticle concentration, the size and number of necks increase, resulting in an increased effective thermal conductivity (ETC) of NTS. The drying temperature is found to have only little influence on the ETC of resultant NTS, while the neck size and spatial distribution become more uniform at higher drying temperature. When reducing the wettability of the top and bottom surfaces of the cavity, the necks shrink in size until completing evacuating at the top and bottom layers, while the size of the necks between filler particles in the middle height of the cavity expands slowly. In consequence, the ETC of NTS drops at an increasing rate. Being able to reveal the underlying multiple mechanisms of two-phase flow, phase change and heat transport, the current numerical study suggests optimal values for the deposition process, with initial nanoparticle concentration over 0.8%, a drying temperature of 60°C and a uniform contact angle of 30° for practical production of NTS.

3D chip stacks↗
NASA NTRS1997

A Novel Silicon Micromachined Integrated MCM Thermal Management System

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Kazmierczak, M. J.↗
NASA NTRS2018

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

microchannel↗
DOE OSTI2022

A novel hardmask-to-substrate pattern transfer method for creating 3D, multi-level, hierarchical, high aspect-ratio structures for applications in microfluidics and cooling technologies

Abstract This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200–300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable—using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods—this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS2000

NASA's 3D Flight Computer for Space Applications

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998. This computer, developed in the 1995-97 time frame, contains many new computer technologies previously never used in deep-space systems. They include: advanced 3D packaging architecture for future low-mass and low-volume avionics systems; high-density 3D packaged chip-stacks for both volatile and non-volatile mass memory: 400 Mbytes of local DRAM memory, and 128 Mbytes of Flash memory; high-bandwidth Peripheral Component Interface (Per) local-bus with a bridge to VME; high-bandwidth (20 Mbps) fiber-optic serial bus; and other attributes, such as standard support for Design for Testability (DFT). Even though this computer system did not complete on time for delivery to the DS1 project, it was an important development along a technology roadmap towards highly integrated and highly miniaturized avionics systems for deep-space applications. This continued technology development is now being performed by NASA's Deep Space System Development Program (also known as X2000) and within JPL's Center for Integrated Space Microsystems (CISM).

Alkalai, Leon↗
NASA NTRS2016

Key Elements of a Low Voltage, Ultracompact Plasma Spectrometer

Taking advantage of technological developments in wafer-scale processing over the past two decades, such as deep etching, 3-D chip stacking, and double-sided lithography, we have designed and fabricated the key elements of an ultracompact 1.5cm (exp 3)plasma spectrometer that requires only low-voltage power supplies, has no microchannel plates, and has a high aperture area to instrument volume ratio. The initial design of the instrument targets the measurement of charged particles in the 3-20keV range with a highly directional field of view and a 100 duty cycle; i.e., the entire energy range Is continuously measured. In addition to reducing mass, size, and voltage requirements, the new design will affect the manufacturing process of plasma spectrometers, enabling large quantities of identical instruments to be manufactured at low individual unit cost. Such a plasma spectrometer is ideal for heliophysics plasma investigations, particularly for small satellite and multispacecraft missions. Two key elements of the instrument have been fabricated: the collimator and the energy analyzer. An initial collimator transparency of 20 with 3deg x 3deg angular resolution was achieved. The targeted 40 collimator transparency appears readily achievable. The targeted energy analyzer scaling factor of 1875 was achieved; i.e.20 keV electrons were selected for only a 10.7V bias voltage in the energy analyzer.

Scime, E. E.↗
NASA NTRS2013

Fabrication Method for LOBSTER-Eye Optics in <110> Silicon

Soft x-ray optics can use narrow slots to direct x-rays into a desirable pattern on a focal plane. While square-pack, square-pore, slumped optics exist for this purpose, they are costly. Silicon (Si) is being examined as a possible low-cost replacement. A fabrication method was developed for narrow slots in <110> Si demonstrating the feasibility of stacked slot optics to replace micropores. Current micropore optics exist that have 20-micron-square pores on 26-micron pitch in glass with a depth of 1 mm and an extent of several square centimeters. Among several proposals to emulate the square pore optics are stacked slot chips with etched vertical slots. When the slots in the stack are positioned orthogonally to each other, the component will approach the soft x-ray focusing observed in the micropore optics. A specific improvement Si provides is that it can have narrower sidewalls between slots to permit greater throughput of x-rays through the optics. In general, Si can have more variation in slot geometry (width, length). Further, the sidewalls can be coated with high-Z materials to enhance reflection and potentially reduce the surface roughness of the reflecting surface. Narrow, close-packed deep slots in <110> Si have been produced using potassium hydroxide (KOH) etching and a patterned silicon nitride (SiN) mask. The achieved slot geometries have sufficient wall smoothness, as observed through scanning electron microscope (SEM) imaging, to enable evaluation of these slot plates as an optical element for soft x-rays. Etches of different angles to the crystal plane of Si were evaluated to identify a specific range of etch angles that will enable low undercut slots in the Si <110> material. These slots with the narrow sidewalls are demonstrated to several hundred microns in depth, and a technical path to 500-micron deep slots in a precision geometry of narrow, closepacked slots is feasible. Although intrinsic stress in ultrathin wall Si is observed, slots with walls approaching 1.5 microns can be achieved (a significant improvement over the 6-micron walls in micro - pore optics). The major advantages of this technique are the potential for higher x-ray throughout (due to narrow slot walls) and lower cost over the existing slumped micropore glass plates. KOH etching of smooth sidewalls has been demonstrated for many applications, suggesting its feasibility for implementation in x-ray optics. Si cannot be slumped like the micropore optics, so the focusing will be achieved with millimeter-scale slot plates that populate a spherical dome. The possibility for large-scale production exists for Si parts that is more difficult to achieve in micropore parts.

Chervenak, James↗
NASA NTRS1994

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Carson, John C.↗
DOE OSTI2025

Performance of the AstroPix Prototype Module for the Barrel Imaging Calorimeter at the ePIC Detector and in Space-Based Payloads

AstroPix is a high-voltage CMOS (HV-CMOS) monolithic active pixel sensor originally developed to enable precision gamma-ray imaging and spectroscopy in the medium-energy regime (~100 keV–100 MeV) based on the groundwork laid by ATLASpix and MuPix. It features a 500 μm pixel pitch, in-pixel amplification and digitization, and low power consumption (~3-4 mW/cm2), making it scalable for large-area, multilayer telescope detector planes. The detectors have a designed dynamic range of 25 keV to 700 keV. With these features, AstroPix meets the requirements of future space-based high-energy telescopes and the imaging layers of the Barrel Imaging Calorimeter (BIC) in the Electron-Proton/Ion Collider (ePIC) detector at the future Electron-Ion Collider (EIC). For the space-based payload, AstroPix is being integrated into sounding rocket and balloon payloads to demonstrate the technical readiness of the devices. For BIC, AstroPix-based imaging layers interleaved within the lead/scintillating-fiber (Pb/SciFi) sampling calorimeter provide granular shower imaging, enabling key performance features such as electron/pion or gamma/neutral pion separation. As part of the ongoing detector R&D efforts, we have been testing various AstroPix_v3 configurations: the single chip, a quad-chip assembly, a three-layer stack of quad chips, and a 9-chip module that represents the smallest prototype unit of the BIC imaging layer. This presentation will highlight recent performance test results from these AstroPix detector configurations.

Kim, Bobae (ORCID:0000000295396815)↗
NASA NTRS1999

3D Chip Scale Package (CSP)

Package/die stacking technology enhances most aspects of electronic systems such as size, weight, speed, yield, and power consumption.

Chip Scale Packaging (CSP) 3D CSP Stack TSOP D2CSP↗
NASA NTRS1993

The Application of Microtechnology to Spacecraft On-Board Computing(abstract)

In this report, we will survey recent advances in chip packaging and stacking techniques that allow miniature computers to be developed for space applications. Several orders of magnitude reduction in mass, volume, and power consumption are possible using these techniques. Moreover, performance improvements can be achieved by increasing the scale of multiprocessing. Most importantly, long-term survivability can potentially be improved by increasing the level of redundancy and fault tolerance.

microtechnology computers multiprocessing packagin↗
NASA NTRS1991

High density packaging and interconnect of massively parallel image processors

This paper presents conceptual designs for high density packaging of parallel processing systems. The systems fall into two categories: global memory systems where many processors are packaged into a stack, and distributed memory systems where a single processor and many memory chips are packaged into a stack. Thermal behavior and performance are discussed.

Carson, John C.↗
NASA NTRS1999

Review of Stack CSP Technologies

CSP is an emerging technology with significant potential growth in stacking. Many of the stacking techniques for conventional packages could be implemented for CSP once materials, process, and system development for finer features are developed.

3D CSP stack CSP Chip Scale Package MCM Mulitchip ↗
NASA NTRS2015

Two-Dimensional Planar Lightwave Circuit Integrated Spatial Filter Array and Method of Use Thereof

A large coherent two-dimensional (2D) spatial filter array (SFA), 30 by 30 or larger, is produced by coupling a 2D planar lightwave circuit (PLC) array with a pair of lenslet arrays at the input and output side. The 2D PLC array is produced by stacking a plurality of chips, each chip with a plural number of straight PLC waveguides. A pupil array is coated onto the focal plane of the lenslet array. The PLC waveguides are produced by deposition of a plural number of silica layers on the silicon wafer, followed by photolithography and reactive ion etching (RIE) processes. A plural number of mode filters are included in the silica-on-silicon waveguide such that the PLC waveguide is transparent to the fundamental mode but higher order modes are attenuated by 40 dB or more.

Ai, Jun↗
NASA NTRS1990

Tunable-Quantum-Well Infrared Detector

Proposed detector of infrared photons based on photon-assisted, resonant quantum-mechanical tunneling between adjacent energy wells in its semiconductor structure. Wavelength adjusted by changing applied voltage. Device contains alternating layers of different seminconductors which form double-quantum-well electron-energy structure. Tunable-quantum-well detectors made on single chip constitutes line imager. Many such devices stacked to form two-dimensional imaging device. Signal-processing circuitry integrated into chip at its lower end. Potential barriers and wells produced by alternating layers of different semiconductor materials. Steepness of slope proportional to applied electric field. Electric field and thicknesses and heights of barriers selected to favor photon-assisted, resonant quantum-mechanical tunneling at chosen photon frequency.

Maserjian, Joseph↗
NASA NTRS1998

GSFC Cutting Edge Avionics Technologies for Spacecraft

With the launch of NASA's first fiber optic bus on SAMPEX in 1992, GSFC has ushered in an era of new technology development and insertion into flight programs. Predating such programs the Lewis and Clark missions and the New Millenium Program, GSFC has spearheaded the drive to use cutting edge technologies on spacecraft for three reasons: to enable next generation Space and Earth Science, to shorten spacecraft development schedules, and to reduce the cost of NASA missions. The technologies developed have addressed three focus areas: standard interface components, high performance processing, and high-density packaging techniques enabling lower cost systems. To realize the benefits of standard interface components GSFC has developed and utilized radiation hardened/tolerant devices such as PCI target ASICs, Parallel Fiber Optic Data Bus terminals, MIL-STD-1773 and AS1773 transceivers, and Essential Services Node. High performance processing has been the focus of the Mongoose I and Mongoose V rad-hard 32-bit processor programs as well as the SMEX-Lite Computation Hub. High-density packaging techniques have resulted in 3-D stack DRAM packages and Chip-On-Board processes. Lower cost systems have been demonstrated by judiciously using all of our technology developments to enable "plug and play" scalable architectures. The paper will present a survey of development and insertion experiences for the above technologies, as well as future plans to enable more "better, faster, cheaper" spacecraft. Details of ongoing GSFC programs such as Ultra-Low Power electronics, Rad-Hard FPGAs, PCI master ASICs, and Next Generation Mongoose processors.

Luers, Philip J.↗