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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

"Glitch Logic" and Applications to Computing and Information Security

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

hardware vulnerabilities↗
NASA NTRS1991

An architecture for designing fuzzy logic controllers using neural networks

Described here is an architecture for designing fuzzy controllers through a hierarchical process of control rule acquisition and by using special classes of neural network learning techniques. A new method for learning to refine a fuzzy logic controller is introduced. A reinforcement learning technique is used in conjunction with a multi-layer neural network model of a fuzzy controller. The model learns by updating its prediction of the plant's behavior and is related to the Sutton's Temporal Difference (TD) method. The method proposed here has the advantage of using the control knowledge of an experienced operator and fine-tuning it through the process of learning. The approach is applied to a cart-pole balancing system.

Berenji, Hamid R.↗
NASA NTRS1972

Design of automata theory of cubical complexes with applications to diagnosis and algorithmic description

The following problems are considered: (1) methods for development of logic design together with algorithms, so that it is possible to compute a test for any failure in the logic design, if such a test exists, and developing algorithms and heuristics for the purpose of minimizing the computation for tests; and (2) a method of design of logic for ultra LSI (large scale integration). It was discovered that the so-called quantum calculus can be extended to render it possible: (1) to describe the functional behavior of a mechanism component by component, and (2) to compute tests for failures, in the mechanism, using the diagnosis algorithm. The development of an algorithm for the multioutput two-level minimization problem is presented and the program MIN 360 was written for this algorithm. The program has options of mode (exact minimum or various approximations), cost function, cost bound, etc., providing flexibility.

Roth, J. P.↗
NASA NTRS2011

Mars Science Laboratory Entry Guidance Improvements for Mars 2018 (DRAFT)

In 2011, the Mars Science Laboratory (MSL) will be launched in a mission to deliver the largest and most capable rover to date to the surface of Mars. A follow on MSL-derived mission, referred to as Mars 2018, is planned for 2018. Mars 2018 goals include performance enhancements of the Entry, Descent and Landing over that of its predecessor MSL mission of 2011. This paper will discuss the main elements of the modified 2018 EDL preliminary design that will increase performance on the entry phase of the mission. In particular, these elements will increase the parachute deploy altitude to allow for more time margin during the subsequent descent and landing phases and reduce the delivery ellipse size at parachute deploy through modifications in the entry reference trajectory design, guidance trigger logic design, and the effect of additional navigation hardware.

Garcia-Llama, Eduardo↗
NASA NTRS1991

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Smith, Edwyn D.↗
NASA NTRS2003

Fuzzy Logic Trajectory Design and Guidance for Terminal Area Energy Management

The second generation reusable launch vehicle will leverage many new technologies to make flight to low earth orbit safer and more cost effective. One important capability will be completely autonomous flight during reentry and landing, thus making it unnecessary to man the vehicle for cargo missions with stringent weight constraints. Implementation of sophisticated new guidance and control methods will enable the vehicle to return to earth under less than favorable conditions. The return to earth consists of three phases--Entry, Terminal Area Energy Management (TAEM), and Approach and Landing. The Space Shuttle is programmed to fly all three phases of flight automatically, and under normal circumstances the astronaut-pilot takes manual control only during the Approach and Landing phase. The automatic control algorithms used in the Shuttle for TAEM and Approach and Landing have been developed over the past 30 years. They are computationally efficient, and based on careful study of the spacecraft's flight dynamics, and heuristic reasoning. The gliding return trajectory is planned prior to the mission, and only minor adjustments are made during flight for perturbations in the vehicle energy state. With the advent of the X-33 and X-34 technology demonstration vehicles, several authors investigated implementing advanced control methods to provide autonomous real-time design of gliding return trajectories thus enhancing the ability of the vehicle to adjust to unusual energy states. The bulk of work published to date deals primarily with the approach and landing phase of flight where changes in heading angle are small, and range to the runway is monotonically decreasing. These benign flight conditions allow for model simplification and fairly straightforward optimization. This project focuses on the TAEM phase of flight where mathematically precise methods have produced limited results. Fuzzy Logic methods are used to make onboard autonomous gliding return trajectory design robust to a wider energy envelope, and the possibility of control surface failures, thus increasing the flexibility of unmanned gliding recovery and landing.

Burchett, Bradley↗
NASA NTRS1980

Pioneer Venus Sounder Probe gas chromatograph

The design logic, construction, function, and data processing of the Pioneer Venus Sounder Probe gas chromatograph instrument are discussed. A gas chromatograph for the analysis of the chemical composition of the lower atmosphere of Venus was included in the Sounder Probe of the Pioneer Venus mission. This paper describes the design logic of the gas chromatograph as constrained by the mission; attention is given to instrument construction, function, and data reduction.

Oyama, V. I.↗
NASA NTRS2009

Efficient Multiplexer FPGA Block Structures Based on G4FETs

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Vatan, Farrokh↗
DOE OSTI2023

Model-based data center cooling controls comparative co-design

This article presents a comparative simulation-based control logic design process. It uses the Control Description Language (CDL) and the ASHRAE Guideline 36 high-performing building control sequences with the Modelica Buildings Library (MBL) to demonstrate a comparative analysis of two control designs for a data center chilled water plant. Details include a description of the closed-loop plant and control design methodology, including sizing and parameterization, base and alternative (Guideline 36) control logic with software implementation structure, and outline of the simulation experimentation process. The selected control designs are paired with comparable chilled water plant configurations. The models include a chiller, a water-side economizer, and an evaporative cooling tower. The plant provides cooling at 27ºC zone supply air temperature to a data center in Sacramento, CA. The comparative simulation results examined the impacts of a selected control logic detail, and present an example model-based design application. Overall, the simulation results showed a 25% annual and a 18% summer energy use reduction for alternative controls. This shows that simulation-based control logic design performance evaluation can improve energy efficiency and resilience aspects of system controls at large.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
NASA NTRS1980

DDL:Digital systems design language

Hardware description languages are valuable tools in such applications as hardware design, system documentation, and logic design training. DDL is convenient medium for inputting design details into hardware-design automation system. It is suitable for describing digital systems at gate, register transfer, and major combinational block level.

Shival, S. G.↗
NASA NTRS1972

Design of automata theory of cubical complexes with applications to diagnosis and algorithmic description

Methods for development of logic design together with algorithms for failure testing, a method for design of logic for ultra-large-scale integration, extension of quantum calculus to describe the functional behavior of a mechanism component-by-component and to computer tests for failures in the mechanism using the diagnosis algorithm, and the development of an algorithm for the multi-output 2-level minimization problem are discussed.

Roth, J. P.↗
NASA NTRS1971

A spacecraft computer repairable via command.

The MULTIPAC is a central data system developed for deep-space probes with the distinctive feature that it may be repaired during flight via command and telemetry links by reprogramming around the failed unit. The computer organization uses pools of identical modules which the program organizes into one or more computers called processors. The interaction of these modules is dynamically controlled by the program rather than hardware. In the event of a failure, new programs are entered which reorganize the central data system with a somewhat reduced total processing capability aboard the spacecraft. Emphasis is placed on the evolution of the system architecture and the final overall system design rather than the specific logic design.

Fimmel, R. O.↗
NASA NTRS1977

Numerical aerodynamic simulation facility preliminary study, volume 2 and appendices

Data to support results obtained in technology assessment studies are presented. Objectives, starting points, and future study tasks are outlined. Key design issues discussed in appendices include: data allocation, transposition network design, fault tolerance and trustworthiness, logic design, processing element of existing components, number of processors, the host system, alternate data base memory designs, number representation, fast div 521 instruction, architectures, and lockstep array versus synchronizable array machine comparison.

Source record↗
DOE OSTI2020

Graph Theory and IC Component Design Analysis

Graph analysis in large integrated circuit (IC) designs is an essential tool for verifying design logic and timing via dynamic timing analysis (DTA). IC designs resemble graphs with each logic gate as a vertex and the conductive connections between gates as edges. Using DTA digital statistical correlations, graph condensation, and graph partitioning, it is possible to identify high-entropy component centers and paths within an IC design. Identification of high-entropy component centers (HECC) enables focused DTA, effectively lowering the computational complexity of DTA on large integrated circuit graphs. In this paper, a devised methodology termed IC layout subgraph component center identification (CCI) is used to identify described. CCI lowers DTA computationally complexity by condensing IC graphs into reduced subgraphs in which dominant logic functions are verified.

42 ENGINEERING↗