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Ball Grid Arrays (BGAs) are now packages of choice especially for higher I/O counts for commercial applications and are also being considered for use in military and aerospace.
Ball Grid Array (BGA) is an important technology for utilizing higher pin counts, without the attendant handling and processing problems of the peripheral leaded packages. They are also robust in processing because of their higher pitch (0.050 inches typical), better lead rigidity, and self-alignment characteristics during reflow processing.
Jet Propulsion Laboratory (JPL) is currently assessing the use of Ball Grid Arrays (BGAs) for National Aeronautics and Space Administration (NASA) spaceflight applications. This work is being funded through NASA Headquarters, Code Q. The objectives are to demonstrate the robustness, quality and reliability of BGAs technology, and to assist in the development of the repidly growing infastructure for this technology.
The Jet Propulsion Laboratory (JPL) is currently assessing the use of Ball Grid Arrays (BGAs) for National Aeronautics and Space Administration (NASA) spaceflight applications. This work is being funded through NASA Headquarters, Code Q. The objectives are to demonstrate the robustness, quality and reliability of BGAs technology, and to assist in the solicited industrial, academic and other related consortia to work together to leverage the related efforts into a synergistic effort. Initial results of these activities will be summarized and presented in this paper.
This viewgraph presentation reviews the inspection techniques for Column Grid Array (CGA) packages. The CGA is a method of chip scale packaging using high temperature solder columns to attach part to board. It is becoming more popular over other techniques (i.e. quad flat pack (QFP) or ball grid array (BGA)). However there are environmental stresses and workmanship challenges that require good inspection techniques for these packages.
Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.
This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies. Acceleration induced failure mechanisms varied from conventional surface mount (SM) failures for CSPs. Examples of unrealistic life projections for other CSPs are also presented. The cumulative cycles to failure for ceramic BGA assemblies performed under different conditions, including plots of their two Weibull parameters, are presented. The results are for cycles in the range of -30 C to 100 C, -55 C to 100 C, and -55 C to 125 C. Failure mechanisms as well as cycles to failure for thermal shock and thermal cycling conditions in the range of -55 C to 125 C were compared. Projection to other temperature cycling ranges using a modified Coffin-Manson relationship is also presented.
This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies.
Diffenent aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included understanding assembly reliability behavior of conventional surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Different aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included the assembly reliability of conventional Surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Spacecraft electronics including those used at the Jet Propulsion Laboratory (JPL), demand production of highly reliable assemblies. JPL has recently completed an extensive study, funded by NASA's code Q, of the interplay between manufacturing defects and reliability of ball grid array (BGA) and surface mount electronic components.
Spacecraft electronics including those used at the Jet Propulsion Laboratory (JPL), demand production of highly reliable assemblies. More than 400 test vehicles were assembled using ceramic and plastic ball grid arrays (BGAs), LCCs, J-leads, and gull wing components.
Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability or future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185oC to +125oC) covers military specifications (-55oC to +100oC), extreme old Martian (-120oC to +115oC), asteroid Nereus (-180oC to +25oC) and JUNO (-150oC to +120oC) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185oC to +125oC) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.
The primary'technical objective of this project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIPD assembled and reworked with lead-free alloys Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with mixed (lead/lead-free) alloys.
In response to concerns about risks from lead-free induced faults to high reliability products, NASA has initiated a multi-year project to provide manufacturers and users with data to clarify the risks of lead-free materials in their products. The project will also be of interest to component manufacturers supplying to high reliability markets. The project was launched in November 2006. The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: (1) Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIP]) assembled and reworked with solder interconnects consisting of lead-free alloys (2) Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of mixed alloys, lead component finish/lead-free solder and lead-free component finish/SnPb solder
The primary technical objective of this project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: (1) Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIP]) assembled and reworked with lead-free alloys, (2) Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with mixed (lead/lead-free) alloys.
Bottom terminated components and quad flat no-lead (BTC/QFN) packages have been extensively used by commercial industry for more than a decade. Cost and performance advantages and the closeness of the packages to the boards make them especially unique for radio frequency (RF) applications. A number of high-reliability parts are now available in this style of package configuration. This report presents a summary of literature surveyed and provides a body of knowledge (BOK) gathered on the status of BTC/QFN and their advanced versions of multi-row QFN (MRQFN) packaging technologies. The report provides a comprehensive review of packaging trends and specifications on design, assembly, and reliability. Emphasis is placed on assembly reliability and associated key design and process parameters because they show lower life than standard leaded package assembly under thermal cycling exposures. Inspection of hidden solder joints for assuring quality is challenging and is similar to ball grid arrays (BGAs). Understanding the key BTC/QFN technology trends, applications, processing parameters, workmanship defects, and reliability behavior is important when judicially selecting and narrowing the follow-on packages for evaluation and testing, as well as for the low risk insertion in high-reliability applications.
Bottom terminated components and quad flat no-lead (BTC/QFN) packages have been extensively used by commercial industry for more than a decade. Cost and performance advantages and the closeness of the packages to the boards make them especially unique for radio frequency (RF) applications. A number of high-reliability parts are now available in this style of package configuration. This report presents a summary of literature surveyed and provides a body of knowledge (BOK) gathered on the status of BTC/QFN and their advanced versions of multi-row QFN (MRQFN) packaging technologies. The report provides a comprehensive review of packaging trends and specifications on design, assembly, and reliability. Emphasis is placed on assembly reliability and associated key design and process parameters because they show lower life than standard leaded package assembly under thermal cycling exposures. Inspection of hidden solder joints for assuring quality is challenging and is similar to ball grid arrays (BGAs). Understanding the key BTC/QFN technology trends, applications, processing parameters, workmanship defects, and reliability behavior is important when judicially selecting and narrowing the follow-on packages for evaluation and testing, as well as for the low risk insertion in high-reliability applications.