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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 343 records · Page 19
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Thermally grown oxide and diffusions for automatic processing of integrated circuits

A totally automated facility for semiconductor oxidation and diffusion was developed using a state-of-the-art diffusion furnace and high temperature grown oxides. Major innovations include: (1) a process controller specifically for semiconductor processing; (2) an automatic loading system to accept wafers from an air track, insert them into a quartz carrier and then place the carrier on a paddle for insertion into the furnace; (3) automatic unloading of the wafers back onto the air track, and (4) boron diffusion using diborane with plus or minus 5 percent uniformity. Processes demonstrated include Wet and dry oxidation for general use and for gate oxide, boron diffusion, phosphorous diffusion, and sintering.

Kennedy, B. W.↗
NASA NTRS1983

Etching Integrated Circuits

20-page report reviews methods available for etching specific layers on wafers and discusses automation techniques and features on one particular automated system. Compares two major etching methods, chemical (wet) and plasma (dry), and discusses areas in need of development. Methods covered include "dip-and-dunk" manual method of chemical etching, automated chemical etching, and plasma etching.

Kennedy, B. W.↗
NASA NTRS1981

Activation energies of thermal annealing of radiation-induced damage in n- and p-channels of CMOS integrated circuits. II

The procedures described by Danchenko et al. (1980) are applied to devices of RCA's Z-process (100,000 rad-hard). A thermal annealing investigation of the Z-process reveals an annealing behavior of the p-channels that is anomalous when compared with the p-channels of the commercial and J-processes. It is noted that the thermal annealing-induced shift of the threshold potential extends far below the original value; this necessitated the development of a new mathematical treatment, the treatment presented in the paper.

Danchenko, V.↗
NASA NTRS1984

Optical Testing of Integrated Circuits

Optical spot-raster scanner produces weighted photoresponse image (PI) of operating CMOS IC. Digital analysis of PI's, which correlates differences in PI's with electrical behavior of IC, shows promise both as 100-percent screening method for use in IC manufacture and as diagnostic tool in IC development.

Erickson, J.↗
NASA NTRS1983

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented highlighting the advantages of distributed amplifier approach compared to the conventional single power source designs.

Anzic, G.↗
NASA NTRS1982

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Woo, D. S.↗
NASA NTRS1984

Development of standardized specifications for screening space level integrated circuits and semiconductors

Standardized methods are established for screening of JAN B microcircuits and JANTXV semiconductor components for space mission or other critical applications when JAN S devices are not available. General specifications are provided which outline the DPA (destructive physical analysis), environmental, electrical, and data requirements for screening of various component technologies. This standard was developed for Air Force Space Division, and is available for use by other DOD agencies, NASA, and space systems contractors for establishing common screening methods for electronic components.

Source record↗
NASA NTRS1984

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented, highlighting the advantages of a distributed amplifier approach compared to the conventional single power source designs. Previously announced in STAR as N84-13399

Anzic, G.↗
NASA NTRS1985

Processing of Image Data by Integrated Circuits

Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.

Armstrong, R. W.↗
NASA NTRS1985

Latchup in CMOS Integrated Circuits

Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.

Soliman, K. A.↗
NASA NTRS1984

Test structures for propagation delay measurements on high-speed integrated circuits

The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

Long, S. I.↗
NASA NTRS1987

APS-Workshop on Characterization of MMIC (Monolithic Microwave Integrated Circuit) Devices for Array Antenna

The IEEE AP-S ADCOM is attempting to expand its educational, tutorial and information exchange activities as a further benefit to all members. To this end, ADCOM will be forming specialized workshops on topics of interest to its members. The first such workshop on Characterization and Packaging of MMIC Devices for Array Antennas was conceived. The workshop took place on June 13, 1986 as part of the 1986 International Symposium sponsored by IEEE AP-S and URSI in Philadelphia, PA, June 9-13, 1986. The workshop was formed to foster the interchange of ideas among MMIC device users and to provide a forum to collect and focus information among engineers experienced and interested in the topic. After brief presentations by the panelists and comments from attendees on several subtopics, the group was divided into working committees. Each committee evaluated and made recommendations on one of the subtopics.

Smetana, Jerry↗
NASA NTRS1985

Single event upset immune integrated circuits for Project Galileo

Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.

Giddings, A. E.↗
NASA NTRS1986

Inverted thermal conversion - GaAs, a new alternative material for integrated circuits

A new type of GaAs is developed which exhibits inverted thermal conversion (ITC); i.e., it converts from conducting to semiinsulating upon annealing at about 850 C. In device fabrication, its low resistivity prior to high-temperature processing differentiates ITC GaAs from the standard semiinsulating GaAs. The ITC characteristics are obtained through control of the concentration of the midgap donor EL2 based on heat treatment and crystal-growth modification. Thus EL2 does not exist in the conducting state of ITC GaAs. Conversion to the semiinsulating state during 850 C annealing is caused by the formation of EL2.

Lagowski, J.↗
NASA NTRS1988

Integrated Circuit For Simulation Of Neural Network

Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

Thakoor, Anilkumar P.↗
NASA NTRS1988

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.↗