A digital V-O-R navigation converter
Large scale MOS IC digital VOR navigation converter, comparing accuracy, size, weight and cost with standard design
Lyons, J. C.↗
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Results for “MOS”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Hardening electronic devices against very high total dose radiation environments
The possibilities and limitations of hardening silicon semiconductor devices to the high neutron and gamma radiation levels and greater than 10 to the eighth power rads required for the NERVA nuclear engine development are discussed. A comparison is made of the high dose neutron and gamma hardening potential of bipolar, metal insulator semiconductors and junction field effect transistors. Experimental data is presented on device degradation for the high neutron and gamma doses. Previous data and comparisons indicate that the JFET is much more immune to the combined neutron displacement and gamma ionizing effects than other transistor types. Experimental evidence is also presented which indicates that p channel MOS devices may be able to meet the requirements.
Buchanan, B.↗
Design, development, fabrication and delivery of register and multiplexer units
Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.
Feller, A.↗
Design, processing, and testing of lsi arrays for space station
The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.
Lile, W. R.↗
Solid state image sensing arrays
The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.
Sadasiv, G.↗
Radiation effects on three low-power microcircuits
Irradiation of several low power circuit elements by Co-60 gamma radiation, low and high energy electrons, and neutrons is discussed. The bipolar circuits were SE480 Q NAND gate, and a micropower frequency divider was used in electronic wrist watches. The MOS device was a dual p-channel MOSFET.
Yamakawa, K. A.↗
Gyrator employing field effect transistors
A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.
Hochmair, E. S.↗
A linear voltage-tunable distributed null device.
A linear voltage-tunable null device was predicted, fabricated, and tested. This filter is conceptually a distributed parameter RC representation of the channel of a MOSFET in a network configuration with a second MOSFET that is treated as a variable resistor. Classical transmission-line theory is used to predict a linear tuning curve with applied bias for the device. This concept was used to design a null device having a null that is linearly tunable in the range of 100 kHz. Such devices were fabricated and tested. Typical MOS processing steps were used and the resulting structures are compatible with the planar technology. The compatibility leads towards extension of this work to different frequency ranges for other specific applications.
Benz, H. F.↗
The NASA computer aided design and test system
A family of computer programs facilitating the design, layout, evaluation, and testing of digital electronic circuitry is described. CADAT (computer aided design and test system) is intended for use by NASA and its contractors and is aimed predominantly at providing cost effective microelectronic subsystems based on custom designed metal oxide semiconductor (MOS) large scale integrated circuits (LSIC's). CADAT software can be easily adopted by installations with a wide variety of computer hardware configurations. Its structure permits ease of update to more powerful component programs and to newly emerging LSIC technologies. The components of the CADAT system are described stressing the interaction of programs rather than detail of coding or algorithms. The CADAT system provides computer aids to derive and document the design intent, includes powerful automatic layout software, permits detailed geometry checks and performance simulation based on mask data, and furnishes test pattern sequences for hardware testing.
Gould, J. M.↗
Basic memory module
Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.
Tietze, F. C.↗
Design, processing, and testing of LSI arrays for space station
The development of a low power, high performance MOS 256-bit random assess memory with beam leads is discussed. Beam lead process development on silicon-on-sapphire (SOS) is also discussed, and initial electrical results on beam lead SOS TA5388 devices are presented. A comparison of the beam leaded 256-bit RAM (TA6567) layout is made with the non-beam leaded version (TA6473).
Schneider, W. C.↗
Design, processing, and testing of LSI arrays for space station
The development of a beam-leaded low power, high performance metal-oxide-semiconductor (MOS), 256-bit random access memory (RAM) was reported. Previous success with the aluminum-gate current-sense version and a silicon-gate voltage-sense version led to the present effort to make a beam-leaded silicon-gate RAM. Some problems unique to the silicon-on-sapphire beam-lead process development are presented. Beam-leaded SOS TA5388 devices using a Si3N4 passivation layer were shown to have good electrical parameters.
Schneider, W. C.↗
Interactive graphical computer-aided design system
System is used for design, layout, and modification of large-scale-integrated (LSI) metal-oxide semiconductor (MOS) arrays. System is structured around small computer which provides real-time support for graphics storage display unit with keyboard, slave display unit, hard copy unit, and graphics tablet for designer/computer interface.
Edge, T. M.↗
Design automation techniques for custom LSI arrays
The standard cell design automation technique is described as an approach for generating random logic PMOS, CMOS or CMOS/SOS custom large scale integration arrays with low initial nonrecurring costs and quick turnaround time or design cycle. The system is composed of predesigned circuit functions or cells and computer programs capable of automatic placement and interconnection of the cells in accordance with an input data net list. The program generates a set of instructions to drive an automatic precision artwork generator. A series of support design automation and simulation programs are described, including programs for verifying correctness of the logic on the arrays, performing dc and dynamic analysis of MOS devices, and generating test sequences.
Feller, A.↗
Quasi-perfect FIFO: Synchronous or asynchronous with application in controller design for the UNICON laser memory
The first-in-first-out memory buffer (FIFO), is an elastic digital memory whose main application is in data buffering between devices operating at different rates. Data written into the top is moved autonomously down toward the bottom of the FIFO to the lowest unoccupied location, and data read from the bottom of the FIFO will cause data from the top to move autonomously down toward the bottom. The FIFO is available in MOS LSI asynchronous form with data rate in the 1 MHz region. The FIFO described yields a simple high-speed iterative implementation, either synchronous of asynchronous. Because of this simple iterative structure, the FIFO is expandable in both number of words and bits per word, and it is attractive from the viewpoint of integrated-circuit production. For the synchronous FIFO, a model was built and successfully used in the controller for the UNICON laser memory. For the asynchronous FIFO, a model was built and also successfully used in a high-performance magnetic tape controller.
Lim, R. S.↗
Electrical and electronic devices and components: A compilation
Components and techniques which may be useful in the electronics industry are described. Topics discussed include transducer technology, printed-circuit technology, solid state devices, MOS transistors, Gunn device, microwave antennas, and position indicators.
Source record↗
Time dependent breakdown in silicon dioxide films
An investigation was conducted regarding the possible existence of a time-dependent breakdown mechanism in thermal oxides of the type used as gate oxide in MOS circuits. Questions of device fabrication are discussed along with details concerning breakdown measurements and the determination of C-V characteristics. A relatively large prebreakdown current observed in one of the cases is related to the time-dependent breakdown.
Svensson, C.↗
A multichannel implantable telemetry system for flow, pressure, and ECG measurements
The design, principles of operation, and performance of an implantable miniaturized (48 cu cm in volume) multiplex telemetry system for simultaneous measurement of up to eight physiological parameters (including cardiovascular data) are described. Integrated circuits are used to reduce the size, complexity, and cost of fabrication. Power consumption is reduced using recently developed complementary MOS devices. PWM technique is selected as it is relatively easy to implement, lends itself to ICs, and provides an accurate means of transmitting data. The system is totally implantable within the chest of a test animal, with no wire penetrating through the skin. It is shown that the described system permits repeated measurement of the physiological effects of a variety of interventions in awake unanesthetized animals.
Fryer, T. B.↗