Engineering topics

Trotter, J. D.

Publications and source records attributed to Trotter, J. D..

13 records

NASA NTRS1982

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗

NASA NTRS1982

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗

NASA NTRS1982

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Trotter, J. D.↗

NASA NTRS1980

Double metalization for VLSI

Postsintering process increases yield of double-layer metal conductors to almost 100 percent. When wafers containing double-metalized chips are sintered, metal layers react with oxide film remaining in insulation layer holes, breaking it up so that it no longer impedes electric current. Cooling also mechanically disrupts oxide film.

Trotter, J. D.↗

NASA NTRS1980

Progress in MOSFET double-layer metalization

Report describes one-year research effort in VLSL fabrication. Four activities are described: theoretical study of two-dimensional diffusion in SOS (silicon-on-sapphire); setup of sputtering system, furnaces, and photolithography equipment; experiments on double layer metal; and investigation of two-dimensional modeling of MOSFET's (metal-oxide-semiconductor field-effect transistors).

Gassaway, J. D.↗

NASA NTRS1980

Models of MOS and SOS devices

Quarterly report describes progress in three programs: dc sputtering machine for aluminum and aluminum alloys; two dimensional computer modeling of MOS transistors; and development of computer techniques for calculating redistribution diffusion of dopants in silicon on sapphire films.

Gassaway, J. D.↗

NASA NTRS1979

Trends and Techniques for Space Base Electronics

Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.

Trotter, J. D.↗

NASA NTRS1979

A study of trends and techniques for space base electronics

The research facilities of the Mississippi State University devoted to microelectronics are described. The fabrication and processing capabilities, computer aided design, and experimental evaluation capabilities are discussed.

Trotter, J. D.↗

NASA NTRS1979

A study of trends and techniques for space base electronics

The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized.

Trotter, J. D.↗

NASA NTRS1978

Post heat treatment effects on double layer metal structures for VLSI applications

The realization of high yield double layer metal systems using wet chemistry processes and the ability to extend yields beyond that attainable with wet chemistry by means of post sintering processes at temperatures below 500 C for potential applications in very large scale integration structures were studied. Yields in excess of 98% and average total contact resistance of less than 150 ohms and 200 ohms were realized for a series of 560 vias of 0.5 X 0.5 mils and 0.2 X 0.2 mils in size, respectively.

Wade, T. E.↗

NASA NTRS1978

A study of trends and techniques for space base electronics

Furnaces and photolithography related equipment were applied to experiments on double layer metal. The double layer metal activity emphasized wet chemistry techniques. By incorporating the following techniques: (1) ultrasonic etching of the vias; (2) premetal clean using a modified buffered hydrogen fluoride; (3) phosphorus doped vapor; and (4) extended sintering, yields of 98 percent were obtained using the standard test pattern. The two dimensional modeling problems have stemmed from, alternately, instability and too much computation time to achieve convergence.

Trotter, J. D.↗

NASA NTRS1978

Trends and techniques for space base electronics

A system was developed for depositing aluminum and aluminum alloys by the D.C. sputtering technique. This system which was designed for a high level of cleanliness and ion monitoring the deposition parameters during film preparation is ready for studying the deposition and annealing parameters upon double level metal preparation. The finite element method was studied for use in the computer modeling of two dimensional MOS transistor structures. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions typical of those used at MSFC. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients. Data are given showing both two dimensional effects and the evolution of the junction depth, sheet resistance and integrated dose with redistribution time.

Gassaway, J. D.↗

NASA NTRS1978

A study of trends and techniques for space base electronics

A sputtering system was developed to deposit aluminum and aluminum alloys by the dc sputtering technique. This system is designed for a high level of cleanliness and for monitoring the deposition parameters during film preparation. This system is now ready for studying the deposition and annealing parameters upon double-level metal preparation. A technique recently applied for semiconductor analysis, the finite element method, was studied for use in the computer modeling of two dimensional MOS transistor structures. It was concluded that the method has not been sufficiently well developed for confident use at this time. An algorithm was developed for confident use at this time. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program which was developed was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients.

Trotter, J. D.↗