Engineering topics
Publications and source records attributed to Lieneweg, U..
Based on technologies developed for the Jet Propulsion Laboratory (JPL) Free-Flying-Magnetometer (FFM) concept, we propose to modify the present design of FFMs for detection of mines and arsenals with large magnetic signature.
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Vertical Bloch Line storage is an emerging technology which has the potential for offering a number of desired data storage attributes in a single chip for space and commercial applications.
Vertical Bloch Line storage is an emerging technology which has the potential for offering a number of desired data storage attributes in a single chip.
VBL technology potentially offers a variety of desirable data storage technology attributes for a variety of applications.
The widths of refractory-gate metal lines were measured as a function of design width W(sub i) and design spacing S(sub j) using an electrical test structure, the Cross-Quad-Bridge.
A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.
A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).
In order to provide watt-level CW output power throughout the millimeter and submillimeter wave region, thousands of solid-state diodes have been monolithically integrated using a metal grid to produce a highly efficient frequency multiplier. Devices considered include GaAs Schottky diodes, thin MOS diodes, and GaAs Barrier-Intrinsic-N(+)diodes. The performance of the present compact low-cost device has been theoretically and experimentally validated.
Wall-level CW solid-state sources in the millimeter-wave region are needed for plasma diagnostics. Monolithic metal-grid arrays containing in excess of 1000 Schottky diodes have produced watt-level output at 66 GHz in a doubler configuration, in excellent agreement with the large-signal predictions of the frequency multiplication. Current efforts are concentrated on fabricating and developing arrays of a novel barrier-intrinsic-N+ (BIN) diode which promise increased performance in a tripler configuration. Initial tests will be made for a configuration where a tripling efficiency of 35 percent at an output frequency of 100 GHz is predicted. Eventual goals are monolithic BIN diode grids operating at 1 THz.
A system is provided for use with wafers that include multiple integrated circuits that include two conductive layers in contact at multiple interfaces. Contact chains are formed beside the integrated circuits, each contact chain formed of the same two layers as the circuits, in the form of conductive segments alternating between the upper and lower layers and with the ends of the segments connected in series through interfaces. A current source passes a current through the series-connected segments, by way of a pair of current tabs connected to opposite ends of the series of segments. While the current flows, voltage measurements are taken between each of a plurality of pairs of voltage tabs, the two tabs of each pair connected to opposite ends of an interface that lies along the series-connected segments. A plot of interface conductances on normal probability chart enables prediction of the yield of good integrated circuits from the wafer.
Basic theoretical and experimental characteristics of a novel 'Thin-MOS' technology, which has promising aspects for integrated high-frequency devices up to several hundred gigahertz are presented. The operation of such devices depends on charge injection into undoped silicon layers of about 1000-A thickness, grown by molecular beam epitaxy on heavily doped substrates, and isolation by thermally grown oxides of about 100-A thickness. Capacitance-voltage characteristics measured at high and low frequencies agree well with theoretical ones derived from uni and ambipolar space-charge models. It is concluded that after oxidation the residual doping in the epilayer is less than approximately 10 to the 16th/cu cm and rises by 3 orders of magnitude at the substrate interface within less than 100 A and that interface states at the oxide interface can be kept low.
Indium arsenide Schottky-Barrier diodes in gallium antimonide substrate mix submillimeter waves, producing much lower frequency output. Integrated diode array has relatively-high signal-to-noise ratio and wide frequency band. Operates at moderate cryogenic temperatures (100 K).
The reduction of the equivalent noise temperature in liquid-nitrogen-cooled submillimeter-wave mixers by the use of Schottky barriers on InSb instead of GaAs is evaluated by an analytical model that assumes limited local oscillator power and matched impedances. The calculations, executed at 1.0 and 1.8 THz, take plasma resonance and skin effect into account. For single and multiple contacts on homogeneous semiconductor materials of optimum doping, the noise of InSb diodes is smaller than that of GaAs diodes by a factor of 3 to 14. A simplified model is used to predict the performance of epitaxial structures as well as alternative materials.
The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.