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At least 19 records

Mechanisms of Protonic Nonvolatile Memory Device

A nonvolatile memory device based on protonic transport in oxides has been proposed. The mobile H+ ions are introduced into the SiO2 layer by annealing Si/SiO2/Si structures in H2 at temperatures greater than 500 deg C. This effect has only been observed for confined oxides that have been annealed at greater than or equal to 1100 C prior to the hydrogenation anneal. This includes buried oxides such as Unibond and SIMOX as well as thermal oxides annealed with a polysilicon cap. An applied field moves the charge within the oxide and the charge stops moving when the field is removed. In a memory device, the hydrogen-annealed oxide is the gate oxide and the position of the mobile charge is sensed by the shift of the I-V curve. Much is still not understood about the motion of the charge across the buried oxide. Previous work has assumed that H+ transport and the time it takes to traverse the oxide is governed by interactions within the bulk of the oxide. Based on parameters that affect the transport time, we conclude that H+ trapping and detrapping at the Si/SiO2 interface are more important than H+ interactions within the oxide bulk. These parameters include the applied field, the H+ concentration and the oxide thickness. One consequence is that projections of device write-time based on the previous assumptions of H+ transport mechanisms may be overly optimistic.

P J Macfarlane↗

A new era of ferroelectric thin films for nonvolatile memories

Ferroelectric films have potential applications in nonvolatile memory devices. In addition to the well-established perovskite-structure oxide ferroelectrics, hafnia- and wurtzite-based ferroelectrics have recently attracted considerable attention because of the improved scalability of the ferroelectric response (down to nanometer thicknesses), their compatibility with silicon fabrication processes, and the availability of deposition methods that realize three-dimensional structures. Furthermore, due to their high compatibility with silicon processes, these are also expected to be used in emerging energy-efficient applications, such as neuromorphic computing and reservoir computing. In this article, we review the fundamentals of hafnia- and wurtzite-based ferroelectrics and their advantages and issues for developing in nonvolatile memory devices. Then, possible emerging applications are discussed.

36 MATERIALS SCIENCE↗

Nonvolatile Memory Solution for Near-Term NASA Missions

Nonvolatile memory (NVM) system that could reliably function in extreme environments is one of the most critical components for many spacecrafts being developed for NASA missions to be launched in next four to seven years. NVM supports the computer system in saving and updating critical state data required for a warm restart after power cycling or in case of a power bus failure. It also provides a power independent mass storage capacity for the scientific data gathered by the instruments. In some cases the window for gathering such data is very small and occurs only once in a given mission. Commercially popular and fully developed Flash NVM technology is inappropriate for many reasons such as the limited read write cycles with slower access speeds, radiation intolerance, higher Single Event Upsets (SEU) rates, etc. It is desirable to have an NVM system based upon a robust cell technology making it immune to the SEUs and with sufficient radiation hardness. Availability of such NVM system seems to be still 5 to 10 years in the future. Meanwhile, it is possible to provide an interim hybrid solution by combining the existing rad-hard technologies. Additional information is contained in the original extended abstract.

Patel, J. U.↗

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

Oldham, Timothy R.↗

SONOS Nonvolatile Memory Cell Programming Characteristics

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

MacLeod, Todd C.↗

Nonvolatile Memory Technology for Space Applications

This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

Oldham, Timothy R.↗

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

A sustainable computing scenario demands more energy-efficient processors. Neuromorphic systems mimic biological functions by employing spiking neural networks for achieving brain-like efficiency, speed, adaptability, and intelligence. Current trends in neuromorphic technologies address the challenges of investigating novel materials, systems, and architectures for enabling high-integration and extreme low-power brain-inspired computing. This review collects the most recent trends in exploiting the physical properties of nonvolatile memory technologies for implementing efficient in-memory and in-device computing with spike-based neuromorphic architectures.

42 ENGINEERING↗

Semiconductor-ferroelectric nonvolatile memory using anomalous high photovoltages in ferroelectric ceramics

A small ferroelectric ceramic element is used with an insulating gate transistor and two diodes as an electrically addressed, nonvolatile memory device which is read out nondestructively. The device uses the anomalous photovoltaic effect in ferroelectric ceramics, an effect in which the polarity and magnitude of photovoltages depend on the direction and magnitude of remanent polarization. Experimental results give memory characteristics. The device could be programmed with pulses as short as 200 ns. There is long-time retention of stored data.

Brody, P. S.↗

Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

plasma-enhanced chemical vapor deposition (PECVD).↗

Nonvolatile memory cells from hafnium zirconium oxide ferroelectric tunnel junctions using Nb and NbN electrodes

Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have attracted interest as non-volatile memory for microelectronics due to ease of integration into back-end-of-line (BEOL) complementary metal oxide semiconductor fabrication. This work examines asymmetric electrode NbN/HZO/Nb devices with 7 nm thick HZO as FTJs in a memory structure, with an output resistance that can be controlled by read and write voltages. The individual FTJs are measured to have a tunneling electroresistance of 10 during the read state without significant filament conduction formation and reasonable ferroelectric performance. Endurance and remanent polarizations of up to 10 5 cycles and 20 μC/cm 2 , respectively, are measured and are shown to be dependent on the cycling voltage. Electrical measurements demonstrate how magnitude of the write pulse can modulate the high state resistance and the read pulse influences both resistance values as well as separation of resistance states. Then, by using two opposite switching FTJ devices in series, a programmable nonvolatile resistor divider is demonstrated. Measurements of these two FTJ unit memory cells show wide applicability to a BEOL microfabrication process for a re-readable, rewritable, and nonvolatile memory cell.

42 ENGINEERING↗

A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths

The dream of achieving a universal memory that can provide robust non-volatile memory states along with low-energy operation has been the key driving force of memory research. Despite dominating the memory market, conventional charge-based memories cannot satisfy these requirements. However, UltraRAM, an oxide-free charge-based memory cell, aims to achieve both of these requirements. This device achieves non-volatility (with an endurance of over 10 7 cycles and a retention of over 1000 years) along with switching at low-voltage (±2.3 V) utilizing a triple-barrier resonant tunneling (TBRT) structure made of InAs/AlSb. In this work, we propose an array design for UltraRAM-based memory devices. Our proposed memory array features separate read-write path and eliminates the possibility of accidentally switching the memory states stored in the array. Moreover, our design allows us to read all the cells in a column in one cycle without imposing any limit on the scalability. Besides, since the read operation in our proposed design is independent of the write mechanism, there is flexibility to optimize the read operation for memory and in-memory computing applications.

Alam, Shamiul↗

Carbon Nanofibers Synthesized on Selective Substrates for Nonvolatile Memory and 3D Electronics

A plasma-enhanced chemical vapor deposition (PECVD) growth technique has been developed where the choice of starting substrate was found to influence the electrical characteristics of the resulting carbon nanofiber (CNF) tubes. It has been determined that, if the tubes are grown on refractory metallic nitride substrates, then the resulting tubes formed with dc PECVD are also electrically conducting. Individual CNFs were formed by first patterning Ni catalyst islands using ebeam evaporation and liftoff. The CNFs were then synthesized using dc PECVD with C2H2:NH3 = [1:4] at 5 Torr and 700 C, and approximately equal to 200-W plasma power. Tubes were grown directly on degenerately doped silicon <100> substrates with resistivity rho approximately equal to 1-5 meterohm-centimeter, as well as NbTiN. The approximately equal to 200-nanometer thick refractory NbTiN deposited using magnetron sputtering had rho approximately equal to 113 microohm-centimeter and was also chemically compatible with CNF synthesis. The sample was then mounted on a 45 beveled Al holder, and placed inside a SEM (scanning electron microscope). A nanomanipulator probe stage was placed inside the SEM equipped with an electrical feed-through, where tungsten probes were used to make two-terminal electrical measurements with an HP 4156C parameter analyzer. The positive terminal nanoprobe was mechanically manipulated to physically contact an individual CNF grown directly on NbTiN as shown by the SEM image in the inset of figure (a), while the negative terminal was grounded to the substrate. This revealed the tube was electrically conductive, although measureable currents could not be detected until approximately equal to 6 V, after which point current increased sharply until compliance (approximately equal to 50 nA) was reached at approximately equal to 9.5 V. A native oxide on the tungsten probe tips may contribute to a tunnel barrier, which could be the reason for the suppressed transport at low biases. Currents up to approximately 100 nA could be cycled, which are likely to propagate via the tube surface, or sidewalls, rather than the body, which is shown by the I-V in figure (a). Electrical conduction via the sidewalls is a necessity for dc NEMS (nanoelectromechanical system) applications, more so than for the field emission applications of such tubes. During the tests, high conductivity was expected, because both probes were shorted to the substrate, as shown by curve 1 in the I-V characteristic in figure (b). When a tube grown on NbTiN was probed, the response was similar to the approximately equal to 100 nA and is represented by curve 2 in figure (b), which could be cycled and propagated via the tube surface or the sidewalls. However, no measureable currents for the tube grown directly on Si were observed as shown by curve 3 in figure (b), even after testing over a range of samples. This could arise from a dielectric coating on the sidewalls for tubes on Si. As a result of the directional nature of ion bombardment during dc PECVD, Si from the substrate is likely re-sputtered and possibly coats the sidewalls.

Kaul, Anupama B.↗