Heavy Ion Testing of Freescale Nano-Crystal Nonvolatile Memory
This viewgraph presentation describes radiation tests of nanocrystal (NC) memory for space systems. A nanocrystal test chip was bombarded by heavy ions from a cyclotron.
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This viewgraph presentation describes radiation tests of nanocrystal (NC) memory for space systems. A nanocrystal test chip was bombarded by heavy ions from a cyclotron.
We present single-event effects testing results from a commercially-available automotive microcontroller. We discuss the difficulties encountered testing with commercially-provided evaluation boards while attempting to classify the complex and varied failure modes of a modern 32-bit microcontroller. This work also describes some of the possible advantages to using off-the-shelf automotive-grade electronics for low-risk aerospace applications.
We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.
Traditionally, accelerator SEE testing is accomplished by removing the tops of packages so that the IC chips are accessible to heavy ions. However, ICs in some advanced packages cannot be de-lidded so a different approach is used that involves grinding and/or chemically etching away part of the package and the chip from the back side. The parts are then tested from the back side with ions having sufficient range to reach the sensitive volume. More recently, the entire silicon substrate in an SOI/SRAM was removed, making it possible to use low-energy ions with shorter ranges. Where removal of part of the package is not possible, facilities at Michigan State, NASA Space Radiation Laboratory, GANIL (France) and GSI (Germany) offer high-energy heavy ions with long ranges so that the ions can reach the devices' sensitive volumes without much change in the LET. Unfortunately, a run will typically involve only one ion species having a single energy and LET due to the long time it takes to tune a new energy. The Variable Depth Bragg Peak (VDBP) method is similar to the above method in that it involves the use of high-energy heavy ions that are able to pass through the packaging material and reach the device, obviating the need to remove the package. However, the method provides a broad range of LETs from a single ion by inserting degraders in the beam that modify the ion energy and, therefore, the LET. The crux of the method involves establishing a fiduciary point for degrader thickness, i.e., where the Bragg peak is located precisely at the sensitive volume in the device, for which the measured SEU cross-section and the ion LET are both also maxima and can be calculated using a Monte-Carlo program, TRIM. Once the fiduciary point has been established, calibrated high density polyethylene (HDPE) degraders are inserted into or removed from the beam to vary the ion LET at the device in a known manner. After each change of degrader thickness, the SEU cross-section is measured and the corresponding LET calculated from the change in degrader thickness. That information is used to generate a plot of cross-section as a function of ion LET. The advantages of this approach are that the part does not have to be de-lidded and a broad range of LETs is available from a single heavy ion without having to go to non-normal angles of incidence to change the "effective" LET. As we will show, it is possible to obtain an entire curve of cross-section versus LET using just two or three ions. Fig. 1 shows curves of cross-section vs LET for a Freescale 4 Mbit SOI/SRAM measured at the 88" Cyclotron at Berkeley and at NSRL. The open symbols are the data obtained from Berkeley for top-side and back-side irradiation. The solid data points are for the data obtained at NSRL using a device for which the package was intact. The data are for Iron and Gold and cover a range of LETs from 4 MeV.cm2/mg to 84 MeV.cm2/mg. The agreement between the data obtained from Berkeley and from NSRL is excellent, demonstrating that the VDBP method is capable of providing accurate values of cross-section versus LET, at least for the 4 Mbit SRAM. Details of the technique will be included in the final presentation.
The Magneto-resistive Random Access Memory (MRAM) from Freescale Semiconductor, MR2A16A, was subjected to heavy ion single event testing. Test results show that this device is sensitive to Single Event Latchup (SEL). The sensitivity of the MRAM was attributed to the complementary metal oxide semiconductor (CMOS) process in which the active portion of this device is constructed. Therefore, the device must be used with caution and may require mitigation techniques if used in a space environment. There was no indication that the MRAM technology itself, the memory element construction, is subject to damage from heavy ions.