SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
The derivation of the circuitry of a field effect transistor (FET) model, the procedure for adapting the model to automated statistical analysis program (ASAP), and the results of applying ASAP on this model are described.
In the case of modern infrared focal planes, one of the major problems is related to the noise contribution of the cooled, impedance-matching device used as the preamplifier stage in the detector electronics system. An ideal preamp device should have the low-noise advantages of a buried-channel device and operate isothermally with the low-temperature detector array. The Ge JFET might provide this ideal device. A testing program with Ge JFETs is discussed. It is concluded that germanium JFETs offer an attractive alternative for cryogenic preamplifier designs. They operate well with high transconductance and low noise at LHe temperatures. It is believed that these devices point the way for the development of large, integrated-array, long wavelength, infrared focal planes which incorporate germanium detectors, germanium load resistors, and germanium preamplifiers within the same monolithic structure.
This five page presentation is grouped into 11 numbered viewgraphs, most of which contain one or more diagrams. Some of the diagrams are accompanied by captions, including: 2) Nanotube FET by Delft, IBM; 3) Nanotube FET/Standard MOSFET; 5) Saturation with carrier-carrier; 7) Electronic properties of carbon nanotube; 8) Theoretical nanotube FET characteristics; 11) Summary: Delft and IBM nanotube FET analysis.
This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).
The development of power Field Effect Transistors (FET) operating in the 20 GHz frequency band is described. The major efforts include GaAs FET device development (both 1 W and 2 W devices), and the development of an amplifier module using these devices.
Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.
A cryogenic cooled, low-noise Field Effect Transistor (FET) amplifier assembly for use at 2.2 to 2.3 GHz was developed for the DSN to meet the requirements of a Very Long Baseline Interferometry (VLBI) upgrade. An amplifier assembly was developed at JPL that uses a commercial closed-cycle helium refrigerator (CCR) to cool a FET amplifier to an operating temperature of 15 K. A cooled probe waveguide-to-coaxial transition similar to that used in the research and development Ultra-Low-Noise S-band Traveling Wave Maser (TWM) is used to minimize input line losses. Typical performance includes an input flange equivalent noise contribution of 14.5 K, a gain slope of less than 0.05 dB/MHz across a bandwidth of 2.2 to 2.3 GHz, an input VSWR of 1.5:1 at 2.25 GHz, and an insertion gain of 45 + or - 1 dB across the bandwidth of 2.2 to 2.3 GHz. Three 2.3 GHz FET/CCR assemblies were delivered to the DSN in the spring of 1987.
The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.
Atomically precise graphene nanoribbons (GNRs) synthesized from the bottom-up exhibit promising electronic properties for high-performance field-effect transistors (FETs). The feasibility of fabricating FETs with GNRs (GNRFETs) has been demonstrated, with ongoing efforts aimed at further improving their performance. However, their long-term stability and reliability remain unexplored, which is as important as their performance for practical applications. In this work, we fabricated short-channel FETs with nine-atom-wide armchair GNRs (9-AGNRFETs). We revealed that the on-state (/ ON ) current performance of the 9-AGNRFETs deteriorates significantly over consecutive full transistor on and off logic cycles, which has neither been demonstrated nor previously considered. To address this issue, we deposited a thin ~10 nm thick atomic layer deposition (ALD) layer of aluminum oxide (Al 2 O 3 ) directly on these devices. The integrity, compatibility, electrical performance, stability, and reliability, of the GNRFETs before and/or after Al 2 O 3 deposition were comprehensively studied. The results indicate that the observed decline in electrical device performance is most likely due to the degradation of contact resistance over multiple measurement cycles. We successfully demonstrated that the devices with the Al 2 O 3 layer operate well up to several thousand continuous full cycles without any degradation. Our study offers valuable insights into the stability and reliability of GNR transistors, which could facilitate their large-scale integration into practical applications.
The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.
A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.
An oriented piezoelectric film incorporated in the insulator region of a silicon insulated-gate field-effect transistor (FET) results in a sensitive high-frequency strain transducer. Theory governing the transducer properties of the piezoelectric insulator FET transducer is presented. Equations are developed which relate the drain current of the device to induced polarizations of the piezoelectric layer. The highest frequency of surface strains to which the FET transducer can respond is determined by the FET frequency response - ultimately by the channel transit time. This frequency can extend to the GHz range. The low-frequency response to applied strain is determined by the dielectric relaxation frequency of the piezoelectric layer.
The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band using GaAs field effect transistors (FETs) was detailed. The major efforts include GaAs FET device development, single-ended amplifier stage, balanced amplifier stage, cascaded stage and radial combiner designs, and amplifier integration and test. A multistage GaAs FET amplifier capable of 8.2 W CW output over the 17.9 to 19.1 GHz frequency band was developed. The GaAs FET devices developed represent state of the art FET power device technology. Further device improvements are necessary to increase the bandwidth to 2.5 GHz, improve dc-to-RF efficiency, and increase power capability at the device level. Higher power devices will simplify the amplifier combining scheme, reducing the size and weight of the overall amplifier.
The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.
Most nonlinear circuit analysis programs that exist today were designed primarily for transient analysis. By incorporating more accurate models in simulation programs, accurate predictions of GaAs field effect transistors (FET) behavior can be accomplished. However, should the designer need to simulate GaAs FETs that operate at high DC-to-RF conversion efficiencies, a more sophisticated model is needed. A relevant and appropriate method is called harmonic-balance, as described by Quere et al.
Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as a class of materials with exceptional electronic, optical, and mechanical properties, making them highly tunable for diverse applications in nanoelectronics, optoelectronics, and catalysis. Here, this review focuses on substitutional doping of TMDs, a key strategy to tailor their properties and enhance device performance, with a focus on its applications over the past five years (2019–2024). We delve into both theoretical and experimental doping approaches, including established methods like chemical vapor transport (CVT) and chemical vapor deposition (CVD) alongside liquid phase exfoliation (LPE) and post-synthesis treatments. Advanced growth techniques are also explored. Challenges like dopant uniformity, concentration control, and stability are addressed. The influence of various dopants on the electronic band structure, carrier concentration, and defect engineering is analyzed in detail. We further explore recent advancements in utilizing doped TMDs for field-effect transistors (FETs), photodetectors, sensors, photovoltaics, optoelectronic devices, energy storage and conversion, and even quantum computers. By examining both the potential and limitations of substitutional doping, this review aims to propel future research and technological advancements in this exciting field.
The metal-to-insulator phase transition (MIT) in two-dimensional (2D) materials under the influence of a gating electric field has revealed interesting electronic behavior and the need for a deeper fundamental understanding of electron transport processes, while attracting much interest in the development of next-generation electronic and optoelectronic devices. Although the mechanism of the MIT in 2D semiconductors is a topic under debate in condensed matter physics, our work demonstrates the tunable percolative phase transition in few-layered MoSe 2 field-effect transistors (FETs) using different metallic contact materials. Here, we attempted to understand the MIT through temperature-dependent electronic transport measurements by tuning the carrier density in a MoSe 2 channel under the influence of an applied gate voltage. In particular, we have examined this phenomenon using the conventional chromium (Cr) and ferromagnetic cobalt (Co) as two metal contacts. For both Cr and Co, our devices demonstrated n-type behavior with a room-temperature field-effect mobility of 16 cm 2 V −1 s −1 for the device with Cr-contacts and 92 cm 2 V −1 s −1 for the device with Co-contacts, respectively. Further, with low temperature measurements at 50 K, the mobilities increased significantly to 65 cm 2 V −1 s −1 for the device with Cr and 394 cm 2 V −1 s −1 for the device with Co-contacts. By fitting our experimental data to the percolative phase transition theory, the temperature-dependent conductivity data show a transition from an insulating-to-metallic behavior at a bias of ∼28 V for Cr-contacts and ∼20 V for Co-contacts. This cross-over of the conductivity can be attributed to an increase in carrier density as a function of the gate bias in temperature-dependent transfer characteristics. By extracting the critical exponents, we find that the transport behavior in the device with Co-contacts aligns closely with the 2D percolation theory. In contrast, the devices with Cr-contacts deviate significantly from the 2D limit at low temperatures.
A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.