Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “double pulse test”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC mosfet -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

42 ENGINEERING↗
DOE OSTI2021

Performance Evaluation and Loss Modeling of WBG Devices based on a Novel Double-Pulse Test Method for Current Source Inverter

Careful measurements of the power device characteristics are necessary to accurately estimate a power converter's losses and efficiency. The conventional double-pulse test (DPT) circuit is a well-known method to implement this laboratory characterization of power devices and power modules. However, the switching characteristics of a power device depend on the power electronics circuit in which it is connected as well as the power circuit's physical layout, in addition to the device's internal structure. Hence, the conventional DPT circuit configuration, which is tailored for a standard voltage-source inverter (VSI), is not well-suited for a current-source inverter (CSI). This paper demonstrates a previously-proposed CSI-based DPT measurement technique that is appropriate for normal CSI operation. The characteristics of SiC MOSFETs and series-connected SiC Schottky diodes used in a CSI are measured using this improved technique while taking temperature effects into account to yield more accurate loss predictions. The CSI losses, including the switching and conduction losses of SiC MOSFETs and SiC Schottky diodes, have been modeled using this approach. The total CSI losses and efficiency have been estimated based on the CSI DPT results and loss models.

42 ENGINEERING↗
DOE OSTI2021

Comprehensive Efficiency Analysis of Current Source Inverter Based on CSI-Type Double Pulse Test and Genetic Algorithm

A current-source inverter (CSI) has a natural output voltage boost feature that can be advantageous for traction applications. Switching frequency is one of the easily-controlled variables that can be adjusted to improve the CSI efficiency at different operating points when the boost function is used. This paper investigates a CSI-based double-pulse test (DPT) measurement that mimics normal operation of the CSI. A loss model of the CSI is developed based on the CSI-type DPT experimental results. The impacts of the switching frequency and voltage boost ratio on the CSI efficiency and output voltage ripple are investigated. Based on the loss model, a genetic algorithm has been introduced that makes it possible to optimize the CSI's switching frequency and modulation index to maximize its efficiency under any desired operating condition.

current-source inverter, genetic algorithm, SPM ma↗
DOE OSTI2020

High-Bandwidth Low-Inductance Current Shunt for Wide-Bandgap Devices Dynamic Characterization

High bandwidth sensors are required to measure the wide-bandgap devices' transient behavior because of their fast switching speed. In addition to high bandwidth, the current sensor must introduce little extra parasitic inductance to the switching power loop. The analysis of conventional shunt resistors shows the key to high bandwidth is the coaxial structure and its parasitic inductance is proportional to its transient heat energy rating. Additionally, by combining the structure of coaxial shunt resistor and alumina substrate surface mount thin film resistors, a novel surface mount coaxial shunt resistor is introduced. Experimental measurement verifies its capability of achieving very high bandwidth while introducing very low parasitic inductance. The design can achieve up to 2.23-GHz measurement bandwidth while keeping its parasitic inductance as low as 0.12 nH. Application in gallium nitride heterojunction-field-effect-transistors double pulse test shows it can faithfully capture the transient current waveform while introducing little interference to the switching behavior.

42 ENGINEERING↗
DOE OSTI2021

Hardware Design of Medium Voltage SiC-Based Modular Multilevel Converters for Grid-Tied Applications

This paper presents a design of a 10 kV silicon carbide (SiC) MOSFET based modular multilevel converter (MMC). The MMC functions as the interconnection between a 24 kV dc bus and a 13. SkV distribution grid. This paper focuses on the hardware design of the MMC and its submodules. The gate driver, auxiliary power supply and bus bur in submodules are major components that need to meet high dv/dt immunity and high insulation voltage requirements. The gate driver achieves over 200 kV/us common mode transient immunity (CMTI). Its associated auxiliary power supply is based on an on-board transformer with over 30 kV insulation capability and 1.4 pF barrier capacitance. The busbar achieves less than 11 kV/cm electric field in the air to avoid partial discharges. Validation tests of the MMC submodule were performed by double pulse tests at 5 kV and buck converter tests at3 kV, 52A (peak). Reliable operations were achieved in validation tests.

auxiliary power supply↗
DOE OSTI2023

PCB-on-DBC GaN Power Module Design with High-Density Integration and Double-Sided Cooling

Lateral gallium nitride (GaN) high-electron-mobility transistors (HEMTs) present better electrical characteristics compared to silicon or silicon carbide devices such as high switching speed and low gate charge, but also present additional challenges on the module design. Here, this paper discusses a high-density GaN power module with double-sided cooling, low inductance, on-package decoupling capacitors, and integrated gate drivers. The GaN dies as well as the gate drive are sandwiched between the printed circuit board (PCB) and direct bonded copper (DBC) substrate to achieve compact loop and double-sided cooling effect. Design considerations and thermal performance are analyzed. A module assembly procedure is presented utilizing the layer-by-layer attachment process. Finally, a 2.7 cm x 1.8 cm half-bridge GaN power module is fabricated and tested, achieving a low power-loop inductance of 1.03 nH, and the overshoot voltage of the switching waveform is less than 5% under a 400-V/25-A double-pulse test. The thermal resistance is 0.32 K/W, verified by simulation and experimental results. The design and assembly process can be generalized and applied to high power applications to achieve high power density and high performance.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

An RC snubber design method to achieve optimized switching noise‐loss trade‐off of cascode GaN HEMTs

Abstract The cascode gallium nitride high electron mobility transistors (GaN HEMTs) are very vulnerable to self‐sustained turn‐off oscillation due to their cascode configuration. This paper presents a design approach for the RC snubber of cascode GaN HEMTs to achieve the optimized noise‐loss trade‐off. At first, an analytical model is proposed to describe the instability of cascode GaN HEMTs‐based test circuits utilizing RC snubber. Based on the model, an analytical approach is proposed to achieve two optimum RC snubber designs S1 and S2. The design S1 can satisfactorily dampen the oscillation with minimum switching losses. The design S2 achieves maximum effective damping on the oscillation at a minimized cost of additional power losses. In the end, the accuracy of the proposed model is validated by the double‐pulse test and good agreement is obtained.

Xue, Peng↗
DOE OSTI2024

Power Layout Design of a GaN HEMTs-Based High-Power High-Efficiency Three-Level ANPC Inverter for 800 V DC Bus System

Multiple commutation paths exist for switching devices in a three-level active neutral point clamped (3L-ANPC) inverter operation based on the selected switching state and current direction. In addition, the capacitive coupling path of the nonswitching device is a key design aspect for enabling high voltage and high current operation of gallium nitride (GaN) switches in 3L-ANPC topology. A comprehensive study of the switching transient events of inner, outer, and clamping devices of 3L-ANPC is presented in this article. The commutation mechanisms for worst-case transient voltage overshoots (TVOs) are identified. A simplified equivalent circuit model is presented to determine the design criteria for the power layout structure's parasitic inductances. A power layout strategy satisfying the design criteria is then proposed using an insulated metal substrate power printed circuit board (PCB) to enable efficient high-power operation. The proposed design minimizes the commutation and capacitive coupling path inductances to 6 nH and 11.5 nH, respectively. This enables the fast switching operation of GaN HEMTs at 800 V dc, 36 A with a low TVO of 31% verified through experimental three-level double pulse test results. Experimental evaluation of a three-phase 3L-ANPC hardware prototype based on the proposed power layout shows 99% efficiency at 800 V, 9.5 kVA and 50 kHz switching frequency. The proposed design achieves a low case-to-ambient thermal resistance of 2.3 °C/W.

42 ENGINEERING↗
DOE OSTI2021

SiC and GaN Devices With Cryogenic Cooling

This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.

42 ENGINEERING↗
DOE OSTI2024

Switching Modes for Reduction of Peak Voltage Transients in GaN-Based Three Level ANPC Inverter

The switching pole voltage can transition between P,0, and N states in a three-level active neutral point clamped (ANPC) inverter. State transitions between 0-P and 0-N can be realized with different switching modes. Three switching modes- Short 1 , Short 2 , and Full are studied considering the effect of capacitive current paths. The role of clamping and inner switch on/off conditions is determined using simplified equivalent circuit models. Short 2 with clamping switch off is beneficial for turn-on overvoltage suppression but results in high turn-off overvoltage. Full mode with a parallel current sharing path is effective for turn-off overvoltage suppression but leads to high turn-on overvoltage. Hence, a Modified Full mode is proposed to achieve the simultaneous objective of overvoltage suppression at both turn-on and turn-off transient during high load currents. This benefits 3L ANPC operation at a low power factor with a high load current at fundamental voltage zero crossing points. Here, a 650V GaN-based three-level ANPC inverter prototype is designed and used to evaluate the switching modes and overvoltage suppression strategies through double pulse tests and continuous operation.

42 ENGINEERING↗
DOE OSTI2025

Packaging a 650V/400A GaN Half-bridge Power Module with Ultra-low Parasitics for Electric Vehicle Drive Applications

This paper proposes a compact and efficient half-bridge power module with three 650 V / 150 A GaN dies in parallel. The power module incorporates a main power printed circuit board (PCB), an interface PCB, and a flex PCB to achieve low parasitics in both power loop and gate-side connection, resolving the issue of high parasitics typically encountered with wire bonding in high-current applications. Additionally, the interface PCB decouples the design constraints between the power loop and the gate loops. The proposed design is optimized with a vertical loop configuration to reduce power loop inductance through magnetic flux cancellation. Finite element analysis indicates that the power loop inductance is 0.58 nH at 100 MHz, while the maximum die junction temperature reaches 131 °C under an ambient temperature of 65 °C and a load current of 385 A. The proposed multi-piece PCB structure reduces the inductance of the drive circuit to minimize EMI and to mitigate false triggering. At the same time, it reduces impedance mismatches across different driver circuits, thereby achieving dynamic current sharing in multi-chip parallel configurations. Under simulation conditions of 400 V / 385 A, the current imbalance among chips was limited to 5 A. A 400 V / 385 A double-pulse test was conducted to experimentally validate the performance of the proposed power module.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2024

Heterogeneous Integration Technologies for High-temperature, High-density, Low-profile Power Modules of Wide Bandgap Devices in Electric Drive Applications (Final Technical Report)

The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Topological Equivalence of VSI and CSI Commutation Cells and Its Application to Switching Resonance Analysis and Damper Design

This paper proposes the concept of the topological equivalence between the commutation cells of a voltage source inverter (VSI) and a current source inverter (CSI) using duality and equivalent circuit transformation techniques. A switching resonance of CSI is analyzed and an effective three-phase RC damper is derived from the dc-link RC damper of VSIs based on the topological equivalence of the VSI and CSI commutation cells. Furthermore, a new three-phase RC damper design framework utilizing the topological equivalence is proposed. Here, experimental results verify that the proposed three-phase RC damper design for CSI significantly reduces the switching resonance and improves the CSI’s output waveform total harmonics distortions (THDs).

42 ENGINEERING↗
DOE OSTI2023

Twelve-crystal prototype of Li 2 MoO 4 scintillating bolometers for CUPID and CROSS experiments

An array of twelve 0.28 kg lithium molybdate (LMO) low-temperature bolometers equipped with 16 bolometric Ge light detectors, aiming at optimization of detector structure for CROSS and CUPID double-beta decay experiments, was constructed and tested in a low-background pulse-tube-based cryostat at the Canfranc underground laboratory in Spain. Performance of the scintillating bolometers was studied depending on the size of phonon NTD-Ge sensors glued to both LMO and Ge absorbers, shape of the Ge light detectors (circular vs. square, from two suppliers), in different light collection conditions (with and without reflector, with aluminum coated LMO crystal surface). The scintillating bolometer array was operated over 8 months in the low-background conditions that allowed to probe a very low, μBq/kg, level of the LMO crystals radioactive contamination by 228 Th and 226 Ra.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

A first test of CUPID prototypal light detectors with NTD-Ge sensors in a pulse-tube cryostat

CUPID is a next-generation bolometric experiment aiming at searching for neutrinoless double-beta decay with ~250 kg of isotopic mass of 100 Mo. It will operate at ~10 mK in a cryostat currently hosting a similar-scale bolometric array for the CUORE experiment at the Gran Sasso National Laboratory (Italy). CUPID will be based on large-volume scintillating bolometers consisting of 100 Mo-enriched Li 2 MoO 4 crystals, facing thin Ge-wafer-based bolometric light detectors. In the CUPID design, the detector structure is novel and needs to be validated. In particular, the CUORE cryostat presents a high level of mechanical vibrations due to the use of pulse tubes and the effect of vibrations on the detector performance must be investigated. In this paper we report the first test of the CUPID-design bolometric light detectors with NTD-Ge sensors in a dilution refrigerator equipped with a pulse tube in an above-ground lab. Light detectors are characterized in terms of sensitivity, energy resolution, pulse time constants, and noise power spectrum. Despite the challenging noisy environment due to pulse-tube-induced vibrations, we demonstrate that all the four tested light detectors comply with the CUPID goal in terms of intrinsic energy resolution of 100 eV RMS baseline noise. Indeed, we have measured 70–90 eV RMS for the four devices, which show an excellent reproducibility. We have also obtained high energy resolutions at the 356 keV line from a 133 Ba source, as good as Ge semiconductor γ detectors in this energy range.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

PSMC Upgrade Development Documentation and Functional Testing

The functional verification consists of verifying that the calibration (a.k.a. gain matching) is accurate and that there is no double pulsing or signal cross talk and interference. The calibration is shown to be satisfactory from the plateau plots on the right. The absence of double pulsing and cross talk can be seen in the time-interval diagram below. Both phenomena are manifested by spikes in the time interval distribution around 1µs to 5µs. No such spike is present.

3-He detector electronics↗
DOE OSTI2023

Immunity Study: Port Impedance Measurement of PMU and PCI testing under EMP

With the increased requirements of real-time grid monitoring, disturbance location, and situation awareness, Phasor Measurement Units (PMUs) have become more critical for the Wide Area Measurement System (WAMS). However, the vulnerability of PMUs has not been well studied, especially under electromagnetic pulse (EMP) scenarios. The stable operation of the power system will be affected directly once EMP damages them. Therefore, studying their immunity to EMP events is urgent and necessary. In this paper, the effective impedance measurement scheme and pulsed current injection (PCI) testing are proposed for the port impedance measurement and immunity levels of PMUs. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Then, the circuit of the pulsed current generator is set to generate a damping sinusoid, and the double exponential wave is applied to the port. Finally, using measured impedance as a generator load, the voltage and current responses of different ports are calculated in the PCI testing simulation. In conclusion, results reveal the characteristics of port impedance, waveforms of voltage and current, and distribution of accumulative energy. The relation between port impedance and the waveforms is discussed.

42 ENGINEERING↗