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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Passivated Contacts for Direct Wafer Product (Final Technical Report)

This TCF project developed a thin-oxide (SiO 2 )/polycrystalline silicon (poly-Si) passivated contact solar cell on CubicPV's (formally 1366 Technologies, Inc.) Direct Wafer® Product (DWP) kerfless wafers. The project used two NREL-developed technologies described in U.S. Patent No. 9,911,873, Hydrogenation of Passivated Contacts and U.S. Patent Application Serial No. 15/890,172, Doped Passivated Contacts . The project was motivated by a potential higher efficiency cell (compared to a PERC cell) using passivated contacts on the ultra-low cost kerfless wafers grown using the Direct Wafer process. The hope was to accelerate market adoption of the cell and wafer by delivering the lowest LCOE in the PV industry. The project tested both n-type and p-type SiO 2 /poly-Si passivated contacts grown by thermal oxidation and plasma enhanced chemical vapor deposition (PECVD) of the poly-Si layer on DWP with varying wafer resistivities. Both deposition techniques are industry standards and thus economically viable methods for commercializing the contacts. The results indicated that both n-type and p-type poly-Si passivated contacts can be formed on polycrystalline DWP wafers, but implied open-circuit voltages (i Voc ) were limited to below 0.65 mV (compared with ~ 730 mV on n-Cz wafers). Diffusion of H to the Si/SiO 2 /poly-Si interface was key to obtaining high i Voc values. In this study, H was diffused from a high-temperature SiN x layer deposited over the poly-Si layer during a high-temperature firing step, similar to one used for screen printed metals. The study concluded that poly-Si passivated contacts on DWP wafers passivated the surface of the wafers as well as PERC passivated surfaces, which use a less expensive dielectric layer stack. The project showed that Direct Wafer Product wafers grown by CubicPV could produce high i Voc values (~0.647 mV), which could produce a cell over 20% efficient with proper processing and metallization. These cells, though not economically viable in 2024 as a stand-alone cell, could be integrated with a wide-bandgap top solar cell to form a two-junction tandem cell that could be viable under certain circumstances. This is because the bottom cell of a 30%, two-terminal tandem only needs to be a 20% cell under one-sun conditions. Thus, the DWP could be an ideal low-cost wafer for tandems. The project also revealed that a TOPCon type cell could be formed on a p-type DWP wafer using a P-diffused emitter and a p-type poly-Si contact. In fact, the p-type version of the poly-Si contact out-performed the n-type version for a variety of wafer resistivities, from highly doped to lowly doped. This curiosity requires more work to understand because on Cz wafers, the n-type poly-Si contact is of much higher quality than the p-type version.

14 SOLAR ENERGY↗
DOE OSTI2025

Wafer-Free Crystalline Silicon Solar Cells (CRADA Final Report)

This CRADA project, based on the DOE Solar Energy Technologies Office (SETO) Solar Prize Voucher program, helped Leap Photovoltaics to develop methodologies to immobilize Si particles by permanently attaching them to an Al-coated substrate and thereby forming carrier-selective electrical contacts to the Si particles. The bigger goal was to help Leap Photovoltaics develop these immobilized and contacted particle arrays into relatively efficient, inexpensive, and industrially relevant solar cells. By using Si particles instead of wafers in a solar cell absorber layer, one can avoid costs associated with growing monocrystalline Si ingots, then diamond-sawing them into wafers, then processing wafers into cells – a mainstream practice in today's high-efficiency Si cell and module technology. Monocrystalline or polycrystalline Si particles can be obtained in various ways: for example, Si kerf from wafer sawing is monocrystalline; recycled Si cell wafers can be ball-milled into particles; particles can be grown using various gas-phase techniques (mostly from SiH4). These Si particles can be assembled onto a substrate and serve as an absorber layer for the solar cell, absorbing photons to generate photocarriers. The challenge with this technique is to collect photocarriers from individual Si particles, with separation of photogenerated electrons to the negative cell’s electrode and positive photogenerated holes to the positive electrode. Therefore, each particle must have two isolated, carrier-selective contacts: one for electrons and one for holes. Plus, particles need to be immobilized onto a solid substrate. The goal of this work was focused on the immobilization of Si particles and creating hole-selective contact to them at the same time, using industrially relevant Si photovoltaic (PV) cell technology: screen printing of Al back-surface field electrodes. This is used in the mainstream Propane Education and Research Council (PERC) technology for hole-collecting contacts at the back of the cell. The work performed at NREL consisted of screen printing of Al metal paste on substrates, spreading Si particles onto it, and thermally processing the structures to form hole-collecting contacts. The final structures were investigated by scanning electron microscopy (SEM) after focused ion beam (FIB) cross-sectioning and polishing. The work was done jointly by NREL staff and Leap Photovoltaics (Leap PV) employees stationed at NREL. The samples were then taken to Leap PV for further processing. Training the Leap PV employee on various NREL techniques (laser cutting, screen printing, thermal processing, characterization) was part of the scope.

14 SOLAR ENERGY↗
DOE OSTI2025

Wafer-scale waveguide sidewall roughness scattering loss characterization by image processing

Photonic integrated circuits (PICs) are vital for developing affordable, high-performance optoelectronic devices that can be manufactured at an industrial scale, driving innovation and efficiency in various applications. Optical loss of modes in thin film waveguides and devices is a critical measure of their performance. Thin film growth, lithography, masking, and etching processes are imperfect processes that introduce significant sidewall and top-surface roughness and cause dominating optical losses in waveguides and photonic structures. This roughness, as perturbations couple light from guided to far-field radiation modes, leads to scattering losses that can be estimated from theoretical models. Typically, with UV-based lithography, sidewall roughness is significantly larger than wafer-top surface roughness. Atomic force microscopy (AFM) imaging measurement gives a 3D and high-resolution roughness profile, but the measurement is inconvenient, costly, and unscalable for large-scale PICs and at wafer-scale. Here, we evaluate the sidewall roughness profile based on 2D high-resolution scanning electron microscope (SEM) imaging. We characterized the loss on two homemade nitride and oxide films on 3-inch silicon wafers with 12 waveguide devices on each and correlated the scattering loss estimated from a 2D image-based sidewall profile and theoretical Payne model. The lowest loss of guided fundamental transverse electric (TE 0 ) mode is found at 0.075 dB/cm at 633 nm across 24 devices, a record at visible wavelength. Our work shows 100% success (edge continuity span exceeding 95% of image width/height) in edge detection in image processing of all images to estimate autocorrelation function and optical mode loss. These demonstrations offer valuable insights into waveguide sidewall roughness and a comparison of experimental and 2D SEM image processing based loss estimations with applications in loss characterization at wafer-scale PICs.

Khurana, Mohit (ORCID:0000000207898672)↗
DOE OSTI2025

Hexagonal Boron Nitride: Physical Properties, Hydride Vapor‐Phase Epitaxy Growth of Large‐Diameter Quasi‐Bulk Wafers and Applications

Hexagonal boron nitride ( h ‐BN), with its ultrawide bandgap and 2D structure, holds an immense promise for advanced semiconductor applications. Scaling bulk crystals to large‐diameter wafers, crucial for complex device fabrication, remains a challenge with high temperature, high pressure, and metal flux solution methods. To address this, recent efforts have focused on hydride vapor‐phase epitaxy (HVPE) for producing large diameter thick h ‐BN quasi‐bulk wafers, reaching hundreds of micrometers. These HVPE‐grown quasi‐bulk crystals exhibit excellent c ‐axis long‐range order. Notably, the in‐plane mobility‐lifetime products for both electrons and holes surpass 10 −4 cm 2 V −1 , which are two orders of magnitude greater than the out‐of‐plane (vertical) values, highlighting the potential for high‐performance devices leveraging superior lateral transport. Lateral detectors fabricated from 100 μm thick B‐10 enriched h‐ BN wafers have achieved a record 60% thermal neutron detection efficiency. Based on its physical properties, h‐ BN appears to be an outstanding material of choice for light‐triggered electronic power switches capable of supporting high ‐ voltage and high ‐ power operations. These recent advancements in large‐diameter h ‐BN quasi‐bulk crystal growth, enabled by HVPE, pave the way for applications spanning deep UV photonics, high‐power electronics, high‐efficiency neutron detection, and quantum information technologies, establishing h ‐BN as both a versatile active semiconductor and an ideal substrate.

Jiang, Hongxing [Department of Electrical and Comp↗
DOE OSTI2025

Broadband unidirectional visible imaging using wafer-scale nano-fabrication of multi-layer diffractive optical processors

We present a broadband and polarization-insensitive unidirectional imager that operates at the visible part of the spectrum, where image formation occurs in one direction, while in the opposite direction, it is blocked. This approach is enabled by deep learning-driven diffractive optical design with wafer-scale nano-fabrication using high-purity fused silica to ensure optical transparency and thermal stability. Our design achieves unidirectional imaging across three visible wavelengths (covering red, green, and blue parts of the spectrum), and we experimentally validated this broadband unidirectional imager by creating high-fidelity images in the forward direction and generating weak, distorted output patterns in the backward direction, in alignment with our numerical simulations. This work demonstrates wafer-scale production of diffractive optical processors, featuring 16 levels of nanoscale phase features distributed across two axially aligned diffractive layers for visible unidirectional imaging. This approach facilitates mass-scale production of ~0.5 billion nanoscale phase features per wafer, supporting high-throughput manufacturing of hundreds to thousands of multi-layer diffractive processors suitable for large apertures and parallel processing of multiple tasks. Beyond broadband unidirectional imaging in the visible spectrum, this study establishes a pathway for artificial-intelligence-enabled diffractive optics with versatile applications, signaling a new era in optical device functionality with industrial-level, massively scalable fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Spatially Precise Light‐Activated Dedoping in Wafer‐Scale MoS 2 Films

2D materials, particularly transition metal dichalcogenides (TMDCs), have shown great potential for microelectronics and optoelectronics. However, a major challenge in commercializing these materials is the inability to control their doping at a wafer scale with high spatial fidelity. Interface chemistry is used with the underlying substrate oxide and concomitant exposure to visible light in ambient conditions for photo-dedoping wafer scale MoS 2 . It is hypothesized that the oxide layer traps photoexcited holes, leaving behind long-lived electrons that become available for surface reactions with ambient air at sulfur vacancies (defect sites) resulting in dedoping. Additionally, high fidelity spatial control is showcased over the dedoping process, by laser writing, and fine control achieved over the degree of doping by modulating the illumination time and power density. This localized change in MoS 2 doping density is very stable (at least 7 days) and robust to processing conditions like high temperature and vacuum. The scalability and ease of implementation of this approach can address one of the major issues preventing the “Lab to Fab” transition of 2D materials and facilitate its seamless integration for commercial applications in multi-logic devices, inverters, and other optoelectronic devices.

14 SOLAR ENERGY↗
DOE OSTI2025

Silicon wafer fracture stress for tracking sensors in particle physics experiments

For the construction of the ATLAS Inner Tracker strip detector, silicon strip sensor modules are glued directly onto carbon fibre support structures using a soft silicone gel. During tests at temperatures below -35°C, several of the sensors were found to crack due to a mismatch in coefficients of thermal expansion between polyimide circuit boards with copper metal layers (glued onto the sensor) and the silicon sensor itself. While module assembly procedures were developed to minimise variations between modules, cold tests showed a wide range of temperatures at which supposedly comparable modules failed. The observed variance (fracture temperatures between -35°C and -70°C) for supposedly comparable modules suggests an undetected variation between modules suspected to be intrinsic to the silicon wafer itself. Therefore, a test programme was developed to investigate the fracture stress of representative sensor wafer cutoffs. This paper presents results for the fracture stress of silicon sensors used in detector modules.

Detector design and construction technologies and ↗
DOE OSTI2026

Uniform Whole Wafer Anisotropic Etching of Structural Ta Thin Films

Tantalum (Ta) has promise as a structural material for micromechanical sensors and actuators. Anisotropic etching of alpha (α) phase Ta is required for micromachining applications. Uniform thickness and etch across a full wafer are desirable features. An experimental investigation is conducted to study plasma etching rate and anisotropy in etching α -Ta in relation to pressure and gas flow ratio. A comparatively low toxicity gas, carbon tetrafluoride (CF4), and argon (Ar) are used. Spectrometry by optical emission spectrometry (OES) and residual gas analysis (RGA) are employed to characterize the plasma to gain insight into the etch mechanisms. At low flow, the etch rate is slow due to an inadequate supply of the etching gas, CF4. The etch rate is also slowed at high flow due to a reduced CF4 residence time. Flow and pressure conditions to achieve a good etch rate and vertical sidewalls are identified and explained by means of a full factorial experiment coupled with emission spectra. Finally, with these conditions, uniform etching of 2.5 μm thick α-Ta across a 4-inch wafer is demonstrated.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Wafer-Scale MgB 2 Superconducting Devices

Progress in superconducting device and detector technologies over the past decade has realized practical applications in quantum computers, detectors for far-infrared telescopes, and optical communications. Superconducting thin-film materials, however, have remained largely unchanged, with aluminum still being the material of choice for superconducting qubits and niobium compounds for high-frequency/high kinetic inductance devices. Magnesium diboride (MgB 2 ), known for its highest transition temperature (T c = 39 K) among metallic superconductors, is a viable material for elevated temperature and higher frequency superconducting devices moving toward THz frequencies. However, difficulty in synthesizing wafer-scale thin films has prevented implementation of MgB 2 devices into the application base of superconducting electronics. Here, we report ultrasmooth (<0.5 nm root-mean-square roughness) and uniform MgB 2 thin (<100 nm) films over 100 mm in diameter and present prototype devices fabricated with these films demonstrating key superconducting properties including an internal quality factor over 10 4 at 4.5 K and high tunable kinetic inductance in the order of tens of pH/sq in a 40 nm thick film. This advancement will enable development of elevated temperature, high-frequency superconducting quantum circuits, and devices.

Boron↗
DOE OSTI2025

Record acceleration of the two-dimensional Ising model using a high-performance wafer-scale engine

The versatility and wide-ranging applicability of the Ising model, originally introduced to study phase transitions in magnetic materials, have made it a cornerstone in statistical physics and a valuable tool for evaluating the performance of emerging computer hardware. Here, we present a novel implementation of the two-dimensional Ising model on Cerebras Wafer-Scale Engine (WSE) – a revolutionary processor that is opening new frontiers in computing. In our deployment of the checkerboard algorithm, we optimized the Ising model to take advantage of the unique WSE architecture. Specifically, we employed a compressed bit representation storing 16 spins on each int16 word, and efficiently distributed the spins over the processing units enabling seamless weak scaling and limiting communications to only immediate neighboring units. Our implementation can handle up to 754 simulations in parallel, achieving an aggregate of over 61.8 trillion flip attempts per second for Ising models with up to 200 million spins. This represents a gain of up to 148 times over previously reported single-devices with a highly optimized implementation on NVIDIA V100 and up to 88 times in productivity compared to NVIDIA H100. Our findings highlight the significant potential of the WSE in scientific computing, particularly in the field of materials modeling.

Ising model↗
DOE OSTI2025

Spectra-Orthogonal Optical Anisotropy in Wafer-Scale Molecular Crystal Monolayers

Controlling the spectral and polarization response of two-dimensional (2D) crystals is vital for developing ultrathin platforms for compact optoelectronic devices. However, independently tuning optical anisotropy and spectral response remains challenging in conventional semiconductors due to the intertwined nature of their lattice and electronic structures. Here, we report spectra-orthogonal optical anisotropy─where polarization anisotropy is tuned independently of spectral response─in wafer-scale, one-atom-thick 2D molecular crystal (2DMC) monolayers synthesized on monolayer transition-metal dichalcogenide (TMD) crystals. Utilizing the concomitant spectral consistency and structural tunability of perylene derivatives, we demonstrate tunable optical polarization anisotropy in 2DMCs with similar spectral profiles, as confirmed by room-temperature scanning tunneling microscopy and cross-polarized reflectance microscopy. Additional angle-dependent analysis of the single-crystal and polycrystalline molecular domains reveals an epitaxial relationship between the 2DMC and TMD. In conclusion, our results establish a scalable, molecule-based 2D crystalline platform for unique and tunable functionalities unattainable in covalent 2D solids.

2D materials↗
DOE OSTI2025

Overcoming Secondary Nucleation of Misoriented Domains during Wafer-Scale Epitaxy of Single-Crystal Graphene on Ge(110)

The wafer-scale synthesis of single-crystal graphene on technologically important substrates is a major challenge inhibiting the development of next-generation devices that harness the exceptional electronic, thermal, and mechanical properties of single-crystal graphene. Here, in this work, the factors controlling the domain orientation of graphene grown epitaxially on Ge(110) are elucidated, and this insight is utilized to produce graphene with minimal polycrystallinity. In the early stages of growth, most graphene islands have unidirectionally aligned lattices. However, we discover a secondary nucleation phenomenon in which misoriented graphene domains nucleate near/from the island edges, introducing defective grain boundaries and significantly increasing polycrystallinity throughout growth. We find that secondary nucleation occurs when islands grow over Ge steps, which form because of an interplay between the island growth and Ge surface topography evolution. Strategies for suppressing secondary nucleation are developed, enabling the synthesis of graphene in which the predominant crystal orientation has high coverage >99% and low rotational spread <0.6°. This work overcomes the irreproducibility of graphene epitaxy on Ge(110) reported in the literature, providing a route toward the large-area synthesis of single-crystal graphene on technologically useful semiconductors.

chemical vapor deposition↗
DOE OSTI2025

Development of an Energy-Efficient and High-Productivity Ammonia Recovery and Removal Process Using Resin-Wafer Electrodeionization

As efforts to develop various energy resources, ammonia energy is emerging as a promising carbon-free fuel alternative. Recovering high-concentration ammonia and ammonium from wastewater potentially offers significant environmental and economic benefits. However, research on recovery technologies for industries such as semiconductors remains limited. This study develops an efficient, energy-saving ammonia recovery technology using Resin Wafer Electrodeionization (RW-EDI), specifically for the semiconductor industry. RW-EDI shows promise for recovering ammonia from high-concentration wastewater. By optimizing parameters, such as voltage and initial concentration, a balance between productivity and energy consumption is achieved. Results indicate that ammonium and fluoride ion transport kinetics are similar, with minimal competition and selectivity values between 0.95 and 1.08. As the initial ammonia/ammonium concentration increases from 500 to 8000 ppm, reaction rate constants and the overall mass transfer coefficient decrease. Increasing the voltage can enhance mass transfer and eliminate barriers. Ion transport primarily occurs in the RW solid phase, accounting for 93.89% of the total current. Additionally, RW-EDI shows superior specific energy consumption within a concentration range of 500 ppm to 8000 ppm, outperforming technologies like electrodialysis by reducing specific energy consumption from 8−15 kWh/kg-NH 4 + to 1.2−2.5 kWh/kg-NH 4 + . This study highlights RW-EDI’s potential for ammonia recovery, providing valuable insights for future applications in wastewater treatment.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Wafer-scale high-k SrTiO 3 dielectrics with rational barrier-layer design for low leakage and high charge density

High-k oxides such as SrTiO 3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO 3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO 3 films on Nb:SrTiO 3 , CaSnO 3 /Nb:SrTiO 3 , and 2-in. SiO 2 /p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO 3 and SiO 2 reduce leakage, but the ultra-wide-bandgap SiO 2 layer enables much higher operating voltages, yielding charge densities exceeding 5 × 10 13 cm −2 at room temperature—more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO 2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering—including wafer-scale integration on Si—provides a clear pathway to achieving higher charge densities in SrTiO 3 -based dielectric devices.

36 MATERIALS SCIENCE↗
DOE OSTI2024

A Scalable & Non-Destructive Characterization Strategy to Study Semiconductor/Dielectric Interfaces and Predict Wafer-Level Device Performance

The defect density present at the dielectric-semiconductor interface in an MOS structure directly influences the channel carrier characteristics in semiconductor devices, especially in wide bandgap material systems used in power devices. While these trap defects are typically quantified through electrical characterization of MOS-capacitor test structures, this treatment offers very little insight into the physical nature of interface defects. Such shortcomings demand a physical characterization strategy to guide fabrication optimization. X-ray photoelectron spectroscopy (XPS) is suggested as a viable technique to determine chemical data for dielectric interfaces formed using atomic layer deposition (ALD) on GaN substrates. Previously, 1-D XPS characterization has confirmed the presence of a Ga x O y interlayer between ALD dielectrics and the GaN substrate. In this work, XPS data is serially collected to form 2-D images of an ALD-Al 2 O 3 /GaN interface as a proof-of-concept experiment for in-situ XPS quality monitoring during ALD processing. The information provided by this work reveals some of the challenges for incorporating XPS characterization as an in-situ strategy during fabrication of GaN-based devices. Separately, electrical mapping of a 2-D array of ALD-Al 2 O 3 /GaN MOS-capacitor devices provide a means to quantify the spatial variations in interface quality across a single wafer. Physical characterization techniques, such as time-of-flight secondary ion mass spectroscopy, provide additional chemical information about the Al 2 O 3 /Ga x O y /GaN structure that complement the electrical mapping results. This analysis shows that a higher Ga x O y content correlates with higher interface state defects for trap energies deep in the band gap.

42 ENGINEERING↗