Sub-Optical Lithography with Nanometer Definition Masks
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Nanometer lithography↗
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Sub-Optical Lithography With Nanometer Definition Masks
Nanometer feature size lithography represents a major paradigm shift for the electronics and micro-electro-mechanical industries. In this paper, we discuss the capacity of dynamic focused reactive ion beam (FIB) etching systems to undertake direct and highly anisotropic erosion of thick evaporated gold coatings on boron-doped silicon X-ray mask membranes. FIB offers a new level of flexibility in micro fabrication, allowing for fast fabrication of X-ray masks, where pattern definition and surface alteration are combined in the same step which eliminates the whole lithographic process, in particular resist, resist development, electro-deposition and resist removal. Focused ion beam diameters as small as 7 nm can be obtained enabling fabrication well into the sub-20 nm regime. In preliminary demonstrations of this X-ray mask fabrication technique 22 nm width lines were milled directly through 0.9 microns of gold and a miniature mass spectrometer pattern was milled through over 0.5 microns of gold. Also presented are the results of the shadow printing, using the large depth of field of synchrotron high energy parallel X-ray beam, of these and other sub-optical defined patterns in photoresist conformally coated over surfaces of extreme topographical variation. Assuming that electronic circuits and/or micro devices scale proportionally, the surface area of devices processed with X-ray lithography and 20 nm critical dimension X-ray masks would be 0.5% that of contemporary devices (350 nm CD). The 20 CD mask fabrication represents an initial effort - a further factor of three reduction is anticipated which represents a further order-of-magnitude reduction in die area.
Hartley, Frank T.↗
Properties Of Plasma-Deposited Amorphous Hydrogenated Carbon
Report reviews experimental research on plasma-deposited films of hydrogenated amorphous carbon. Such films exhibit electrical resistivity, semi-transparency, mechanical hardness, and chemical inertness. Useful as gate dielectrics and passivating layers in semiconductor devices, insulators for metal/insulator/metal devices, and masks in nanometer lithography. Show promise as wear-resistant, hard solid lubricating coats for bearings and optical components.
Miyoshi, Kazuhisa↗
Nanometer X-ray Lithography
New developments for X-ray nanomachinging include pattern transfer onto non-planar surfaces coated with eletrodeposited resists using synchrotron radion X-rays through extremely high-resolution masks made by chemically assisted focused ion beam lithography.
X-rays↗
Chemical Vapor-Deposited (CVD) Diamond Films for Electronic Applications
Diamond films have a variety of useful applications as electron emitters in devices such as magnetrons, electron multipliers, displays, and sensors. Secondary electron emission is the effect in which electrons are emitted from the near surface of a material because of energetic incident electrons. The total secondary yield coefficient, which is the ratio of the number of secondary electrons to the number of incident electrons, generally ranges from 2 to 4 for most materials used in such applications. It was discovered recently at the NASA Lewis Research Center that chemical vapor-deposited (CVD) diamond films have very high secondary electron yields, particularly when they are coated with thin layers of CsI. For CsI-coated diamond films, the total secondary yield coefficient can exceed 60. In addition, diamond films exhibit field emission at fields orders of magnitude lower than for existing state-of-the-art emitters. Present state-of-the-art microfabricated field emitters generally require applied fields above 5x10^7 V/cm. Research on field emission from CVD diamond and high-pressure, high-temperature diamond has shown that field emission can be obtained at fields as low as 2x10^4 V/cm. It has also been shown that thin layers of metals, such as gold, and of alkali halides, such as CsI, can significantly increase field emission and stability. Emitters with nanometer-scale lithography will be able to obtain high-current densities with voltages on the order of only 10 to 15 V.
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Large-area fabrication of nanometer-scale features on GaN using e-beam lithography
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Firat Yasar↗
Laser Material Processing for Microengineering Applications
The processing of materials via laser irradiation is presented in a brief survey. Various techniques currently used in laser processing are outlined and the significance to the development of space qualified microinstrumentation are identified. In general the laser processing technique permits the transferring of patterns (i.e. lithography), machining (i.e. with nanometer precision), material deposition (e.g., metals, dielectrics), the removal of contaminants/debris/passivation layers and the ability to provide process control through spectroscopy.
Helvajian, H.↗
Magnetic Calorimeter Arrays with High Sensor Inductance and Dense Wiring
We describe prototype arrays of magnetically coupled microcalorimeters fabricated with an approach scalable to very large format arrays. The superconducting interconnections and sensor coils have sufficiently low inductance in the wiring and sufficiently high inductance in the coils in each pixel, to enable arrays containing greater than 4000 sensors and 100,000 X-ray absorbers to be used in future astrophysics missions such as Lynx. We have used projection lithography to create submicron patterns (e.g., 400-nanometer-lines and spaces) in our niobium sensor coils and wiring, integrated with gold-erbium sensor films and gold X-ray absorbers. Our prototype devices will explore the device physics of metallic magnetic calorimeters as feature sizes are reduced to nanoscale.
Magnetism↗
Carbon Nanotube Scanning Probe for Surface Profiling of DUV and 193 nm Photoresist Pattern
The continual scaling down of semiconductors to 100 nm and below necessitates a characterization technique to resolve high aspect ratio features in the nanoscale regime. This paper reports the use of atomic force microscope coupled with high aspect ratio multi-walled carbon nanotube scanning probe tip for the purpose of imaging surface profile of photoresists. Multi-walled carbon nanotube tips used in this work are 5-10 nm in diameter and about a micron long. Their exceptional mechanical strength and ability to reversibly buckle enable to resolve steep, deep nanometer-scale features. Images of photoresist patterns generated by 257 nm interference lithography as well as 193 nm lithography are presented to demonstrate multi-walled carbon nanotube scanning probe tip for applications in metrology.
Nguyen, Cattien V.↗
Artifacts for Calibration of Submicron Width Measurements
Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.
Grunthaner, Frank↗
Ion Milling On Steps for Fabrication of Nanowires
Arrays of nanowires having controlled dimensions can now be fabricated on substrates, optionally as integral parts of multilayer structures, by means of a cost-effective, high-yield process based on ion milling on steps. Nanowires made, variously, of semiconductors or metals are needed as components of sensors and high-density electronic circuits. Unlike prior processes used to fabricate nanowires, the present process does not involve electron-beam lithography, manipulation of nanoscopic objects by use of an atomic-force microscope, or any other technique that is inherently unsuitable for scaling up to mass production. In comparison with the prior processes, this process is rapid and simple. Wires having widths as small as a few tens of nanometers and lengths as long as millimeters have been fabricated by use of this process. The figure depicts a workpiece at different stages of the process. A silicon dioxide substrate is coated with a photoresist or poly(methyl methacrylate) [PMMA] to a thickness of as much as 500 nm. The photoresist or PMMA is patterned to form edges where wires are to be formed. A metal - either Pt or Ti - is deposited, by sputtering, to a thickness of as much as 200 nm. By ion milling at normal incidence, the thickness of the metal deposit is reduced until the only metal that remains is in the form of wall-like nanowires along the edges of the photoresist or PMMA. Finally, an oxygen plasma is used to remove the photoresist or PMMA, leaving only the nanowires on the substrate.
Yun, Minhee↗
Nanomanipulation and Lithography for Carbon Nanotube Based Nondestructive Evaluation Sensor Development
Carbon nanotubes (CNTs) offer great potential for advanced sensor development due to the unique electronic transport properties of the material. However, a significant obstacle to the realization of practical CNT devices is the formation of reliable and reproducible CNT to metallic contacts. In this work, scanning probe techniques are explored for both fabrication of metallic junctions and positioning of singlewalled CNTs across these junctions. The use of a haptic force feedback interface to a scanning probe microscope is used to enable movement of nanotubes over micron length scales with nanometer precision. In this case, imaging of the surface is performed with light or intermittent contact to the surface. Increased tip-to-sample interaction forces are then applied to either create junctions or position CNTs. The effect of functionalization of substrate surfaces on the movement and tribology of the materials is also studied. The application of these techniques to the fabrication of CNT-based sensors for nondestructive evaluation applications is discussed.
Wincheski, Buzz↗
Growing Cobalt Silicide Columns In Silicon
Codeposition by molecular-beam epitaxy yields variety of structures. Proposed fabrication process produces three-dimensional nanometer-sized structures on silicon wafers. Enables control of dimensions of metal and semiconductor epitaxial layers in three dimensions instead of usual single dimension (perpendicular to the plane of the substrate). Process used to make arrays of highly efficient infrared sensors, high-speed transistors, and quantum wires. For fabrication of electronic devices, both shapes and locations of columns controlled. One possible technique for doing this electron-beam lithography, see "Making Submicron CoSi2 Structures on Silicon Substrates" (NPO-17736).
Fathauer, Obert W.↗
Fabrication of nano-gap electrode arrays by the construction and selective chemical etching of nano-crosswire stacks
Methods of fabricating nano-gap electrode structures in array configurations, and the structures so produced. The fabrication method involves depositing first and second pluralities of electrodes comprising nanowires using processes such as lithography, deposition of metals, lift-off processes, and chemical etching that can be performed using conventional processing tools applicable to electronic materials processing. The gap spacing in the nano-gap electrode array is defined by the thickness of a sacrificial spacer layer that is deposited between the first and second pluralities of electrodes. The sacrificial spacer layer is removed by etching, thereby leaving a structure in which the distance between pairs of electrodes is substantially equal to the thickness of the sacrificial spacer layer. Electrode arrays with gaps measured in units of nanometers are produced. In one embodiment, the first and second pluralities of electrodes are aligned in mutually orthogonal orientations.
Son, Kyung-Ah↗
New Insights on Subsurface Imaging of Carbon Nanotubes in Polymer Composites via Scanning Electron Microscopy
Despite many studies of subsurface imaging of carbon nanotube (CNT)-polymer composites via scanning electron microscopy (SEM), significant controversy exists concerning the imaging depth and contrast mechanisms. We studied CNT-polyimide composites and, by threedimensional reconstructions of captured stereo-pair images, determined that the maximum SEM imaging depth was typically hundreds of nanometers. The contrast mechanisms were investigated over a broad range of beam accelerating voltages from 0.3 to 30 kV, and ascribed to modulation by embedded CNTs of the effective secondary electron (SE) emission yield at the polymer surface. This modulation of the SE yield is due to non-uniform surface potential distribution resulting from current flows due to leakage and electron beam induced current. The importance of an external electric field on SEM subsurface imaging was also demonstrated. The insights gained from this study can be generally applied to SEM nondestructive subsurface imaging of conducting nanostructures embedded in dielectric matrices such as graphene-polymer composites, silicon-based single electron transistors, high resolution SEM overlay metrology or e-beam lithography, and have significant implications in nanotechnology.
Zhao, Minhua↗
Fabrication of Buried Nanochannels From Nanowire Patterns
A method of fabricating channels having widths of tens of nanometers in silicon substrates and burying the channels under overlying layers of dielectric materials has been demonstrated. With further refinement, the method might be useful for fabricating nanochannels for manipulation and analysis of large biomolecules at single-molecule resolution. Unlike in prior methods, burying the channels does not involve bonding of flat wafers to the silicon substrates to cover exposed channels in the substrates. Instead, the formation and burying of the channels are accomplished in a more sophisticated process that is less vulnerable to defects in the substrates and less likely to result in clogging of, or leakage from, the channels. In this method, the first step is to establish the channel pattern by forming an array of sacrificial metal nanowires on an SiO2-on-Si substrate. In particular, the wire pattern is made by use of focused-ion-beam (FIB) lithography and a subsequent metallization/lift-off process. The pattern of metal nanowires is then transferred onto the SiO2 layer by reactive-ion etching, which yields sacrificial SiO2 nanowires covered by metal. After removal of the metal covering the SiO2 nanowires, what remains are SiO2 nanowires on an Si substrate. Plasma-enhanced chemical vapor deposition (PECVD) is used to form a layer of a dielectric material over the Si substrate and over the SiO2 wires on the surface of the substrate. FIB milling is then performed to form trenches at both ends of each SiO2 wire. The trenches serve as openings for the entry of chemicals that etch SiO2 much faster than they etch Si. Provided that the nanowires are not so long that the diffusion of the etching chemicals is blocked, the sacrificial SiO2 nanowires become etched out from between the dielectric material and the Si substrate, leaving buried channels. At the time of reporting the information for this article, channels 3 m long, 20 nm deep, and 80 nm wide (see figure) had been fabricated by this method.
Choi, Daniel↗
A New Process for Fabricating Random Silicon Nanotips
An improved process for the fabrication of random arrays of silicon nanotips has been demonstrated to be feasible. Relative to other such processes, this process offers advantages of low cost and simplicity. Moreover, this process can readily be combined with other processes used to fabricate integrated circuits and other monolithic silicon structures. Arrays of silicon nanotips are subjects of research and development efforts directed toward utilizing them as field emitters in flat-panel displays, vacuum microelectronics, and microwave devices. Other silicon-nanotip-fabrication processes developed thus far predominantly include lithography, etching, and/or elaborate deposition steps followed by oxide sharpening steps and are both process intensive as well as expensive. In addition to being cheaper and simpler, the present process can efficiently produce silicon nanotips that range in height from a few microns to several tens of microns and are distributed over large areas. The process mentioned here can be summarized as consisting of (1) the growth of micro-etch masks on a silicon substrate, followed by (2) etching away of the masks, along with some of the substrate, to make an array of sharp tips. In the first step of the process, a cleaned silicon substrate is subjected to reactive ion etching (RIE) in a certain mixture of oxygen and carbon tetrafluoride under radio-frequency excitation. This process step results in the growth of fluorine based compounds in the form of stumps randomly distributed on the substrate. These stumps are known in the art as polymer RIE grass. The dimensions of these stumps are of the order of hundreds of nanometers, the exact values depending on process time and gas composition. The areal density of the stumps decreases with increasing process time as they grow and merge with neighboring stumps. These stumps constitute the micro-etch masks for the next step of the process. In the second step of the process, the substrate covered with the microetch masks is subjected to deep reactive ion etching (DRIE) process, which consists of cycles of reactive ion etching alternating with passivation (the Bosch process). The gas used in the etching substeps is sulfur hexafluoride (SF6); the gas used in the passivation substeps is octafluorocyclobutane (C4F8). The portions of the substrate directly under the RIE grass stubs are etched more slowly than are the portions between the stubs. Hence, what remains at the end of the process, after the stubs and parts of the substrate have been etched away, are silicon spikes where the stubs were (see figure). In a variation of the process, one starts with a silicon or silicon-on-insulator substrate with the intent to etch through the full thickness of the substrate. That is to say, one chooses the thickness so that the DRIE step releases individual nanotips. Such individual silicon nanotips may have utility as microscopic probes in biomedical applications.
Manohara, Harish↗
Growing Aligned Carbon Nanotubes for Interconnections in ICs
A process for growing multiwalled carbon nanotubes anchored at specified locations and aligned along specified directions has been invented. Typically, one would grow a number of the nanotubes oriented perpendicularly to a silicon integrated-circuit (IC) substrate, starting from (and anchored on) patterned catalytic spots on the substrate. Such arrays of perpendicular carbon nanotubes could be used as electrical interconnections between levels of multilevel ICs. The process (see Figure 1) begins with the formation of a layer, a few hundred nanometers thick, of a compatible electrically insulating material (e.g., SiO(x) or Si(y)N(z) on the silicon substrate. A patterned film of a suitable electrical conductor (Al, Mo, Cr, Ti, Ta, Pt, Ir, or doped Si), having a thickness between 1 nm and 2 m, is deposited on the insulating layer to form the IC conductor pattern. Next, a catalytic material (usually, Ni, Fe, or Co) is deposited to a thickness between 1 and 30 nm on the spots from which it is desired to grow carbon nanotubes. The carbon nanotubes are grown by plasma-enhanced chemical vapor deposition (PECVD). Unlike the matted and tangled carbon nanotubes grown by thermal CVD, the carbon nanotubes grown by PECVD are perpendicular and freestanding because an electric field perpendicular to the substrate is used in PECVD. Next, the free space between the carbon nanotubes is filled with SiO2 by means of CVD from tetraethylorthosilicate (TEOS), thereby forming an array of carbon nanotubes embedded in SiO2. Chemical mechanical polishing (CMP) is then performed to remove excess SiO2 and form a flat-top surface in which the outer ends of the carbon nanotubes are exposed. Optionally, depending on the application, metal lines to connect selected ends of carbon nanotubes may be deposited on the top surface. The top part of Figure 2 is a scanning electron micrograph (SEM) of carbon nanotubes grown, as described above, on catalytic spots of about 100 nm diameter patterned by electron-beam lithography. These and other nanotubes were found to have lengths ranging from 2 to 10 m and diameters ranging from 30 to 200 nm, the exact values of length depending on growth times and conditions and the exact values of diameter depending on the diameters and thicknesses of the catalyst spots. The bottom part of Figure 2 is an SEM of an embedded array of carbon nanotubes after CMP.
Li, Jun↗