Memory Seeds Enable High Structural Phase Purity in 2D Perovskite Films for High-Efficiency Devices
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99 GENERAL AND MISCELLANEOUS↗
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Results for “Memory device”
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Systems and methods for shock-resistant memory devices
A shock-resistant memory device comprises a housing and a memory module. The memory module is disposed within the housing and surrounded by potting material to protect the memory module from damage during a shock event. The housing can include a port that accommodates a data connection between the memory module and a sensor from which data is desirably received by the memory module. During a shock event the connection between the memory module and the sensor may be severed, but data stored in the memory module can be retained in the memory module which is protected by the housing. To facilitate retrieval of the memory device subsequent to a shock event, a balloon can be affixed to the housing. The balloon can be configured to inflate subsequent to the shock event so that the shock-resistant memory device does not sink in water and to make the memory device more visible for recovery.
42 ENGINEERING↗
GASNet-EX Memory Kinds: Support for Device Memory in PGAS Programming Models
There is an emerging need for adaptive, lightweight communication in irregular HPC applications at exascale, where GPU accelerators provide the majority of available compute cycles. To address this need, Lawrence Berkeley National Lab is developing a programming system to support distributed-memory HPC application development using the Partitioned Global Address Space (PGAS) model. This work includes two major components: UPC++ and GASNet-EX. UPC++ is a C++ template library providing Remote Memory Access (RMA) and Remote Procedure Call (RPC) communication interfaces. GASNet-EX is a portable, high-performance communication middleware library, used by the implementations of UPC++ and many other PGAS programming models. We describe recent advances in GASNet-EX to efficiently implement zero-copy Remote Memory Access (RMA) communication to and from memory on accelerator devices such as GPUs. We demonstrate performance improvements via benchmark results from UPC++ (on Summit) and the Legion programming system (on DGX-1), both using GASNet-EX for communication.
Hargrove, Paul H↗
Nanometer scale nonvolatile memory device and method for storing binary and quantum memory states
Example implementations include an electronic memory device with a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer, and a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer. Example implementations also include a method of depositing graphite crystals onto a substrate to form a gate bottom layer, depositing BN crystals onto the graphite bottom layer to form a BN bottom layer, depositing tungsten ditelluride (WTe2) crystals onto the BN bottom layer to form a metallic layer, depositing the BN crystals onto the BN bottom layer and the metallic layer to form a BN top layer, and depositing the graphite crystals onto the BN top layer to form a gate top layer.
Xiao, Jun↗
Bias control for a memory device
Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.
97 MATHEMATICS AND COMPUTING↗
Bias control for a memory device
Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.
Walker, Dean↗
Zoned namespaces for computing device main memory
Disclosed in some examples are methods, systems, memory devices, memory controllers, and machine-readable mediums which provide for reserving physical memory device resources to specific execution units. Execution units may include processes, threads, virtual machines, functions, procedures, or the like. Physical memory device resources may include channels, modules, ranks, banks, bank groups, and the like. For example, a physical memory device resource that is reservable may be a smallest unit that allows for parallel access with another of the same size unit.
Sheridan, Patrick Michael↗
Characterization of Memory Devices for Energy Efficient Analog In-Memory Neural Computing at the Edge.
Abstract not provided.
Marinella, Matthew↗
Ion beam etching dependence of spin-orbit torque memory devices with switching current densities reduced by Hf interlayers
We report on the fabrication of nanoscale, three-terminal in-plane spin–orbit torque switching devices with low switching current densities. Critical parameters in the fabrication process, including the ion beam etching angle and time, were optimized to avoid fabrication defects and improve device yield. Measurements of the magnetic field and current-induced switching behavior of the tunnel junctions demonstrate a sensitivity to the nanopillar aspect ratio, which dictates the nanopillars’ anisotropy and thermal stability. Additionally, we show that the current density required for switching can be reduced and the device thermal stability increased by inserting Hf interlayers into the heterostructure. Micromagnetic simulations are generally consistent with the experimentally observed switching behavior, suggesting an increase in the interfacial perpendicular anisotropy at the CoFeB/MgO interface and the reduction in the Dzyaloshinskii–Moriya interaction at the W/CoFeB interface by the Hf interlayers.
36 MATERIALS SCIENCE↗
Electron Doping-Induced Metal–Insulator Transition in LaNiO 3 and Memory Devices
LaNiO 3 (LNO) is the only rare-earth nickelate that does not undergo a temperature-driven insulator-metal transition. Here, we report the successful deposition of epitaxial LNO thin films on LaAlO 3 substrates by a chemical solution deposition method. We report a metal-insulator transition driven by electron doping from hydrogen using catalytic Pd electrodes. A series of in-plane devices with LNO thin films and Pd-Au as the two working terminals were designed and fabricated by photolithography. Further, we report their resistance switching behavior and synaptic multiresistance states under voltage pulses. The results demonstrate the universality of electron doping-driven phase transitions in the rare-earth nickelates and their relevance to emerging memory and computing technologies.
37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
Controlling reversible phase transitions in rare-earth nickelates for novel memory devices
Resistive switching in correlated complex oxides is lucrative for emerging applications in neuromorphic computing, and densely scaled non-volatile memory. Electrical conductance of such complex oxides can be controllable switched across multiple orders of magnitude by either (a) electroforming a conduction channel (e.g., in tungsten oxide), or (b) inducing Mott-Hubbard transition (e.g., in rare-earth nickelates)– both via controlled migration of defects (such as oxygen vacancies) under applied bias. Nevertheless, the promise of such defect-driven electronic transitions are far from realized due to a lack of fundamental understanding of the atomic-scale processes that underlie migration and spatiotemporal evolution of oxygen vacancies over nano-to-mesoscopic length/timescales under applied electric field. In this project, we employ a synergistic integration of density functional theory (DFT) calculations, ab initio/classical molecular dynamics (AIMD/CMD) simulations, machine learning (ML), precision synthesis, and multi-modal X-ray imaging experiments to address this knowledge gap. Such an integrated approach offers to elucidate the correlations between subtle structural distortion and oxidation states; treat localized charge carriers; describe defect/ion transport in the presence of electric field; and, in turn, greatly advance the current understanding of microstructural evolution in complex oxides under applied bias. The fundamental knowledge gained from this work will enable precise control over hierarchical defect structures and unravel new routes to manipulate resistance states in complex oxides. This, in turn, will accelerate design of novel devices with desired set of neural functionalities, and high-speed densely-scaled resistive random access memory technologies.
36 MATERIALS SCIENCE↗
Effects of Total Ionizing Dose on PEDOT/PSS Organic Memory Devices (Poster).
Abstract not provided.
Bennett, Christopher H↗
Method and apparatus for data protection in memory devices
An apparatus and method for efficiently transmitting data are described. A transmitter sends data to a receiver. An encoder of the transmitter divides a received first block of data into multiple sub-blocks. The encoder selects a portion of each sub-block to compare to one another. A portion in a particular sub-block has a same offset and a same size as other portions of other sub-blocks. If the encoder determines the multiple portions match one another, the encoder sends, to the receiver, a second block of data corresponding to the first block of data. The second block of data has a same size as a size of the received first block of data, and the second block of data includes security data from one of multiple error correction schemes. Therefore, the second block of data provides security without increasing an amount of data to transmit.
SeyedzadehDelcheh, SeyedMohammad↗
Memory access statistics monitoring
Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
Roberts, David A.↗
Antiferromagnetic memory storage devices from magnetic transition metal dichalcogenides
Switchable antiferromagnetic (AFM) memory devices are provided based on magnetically intercalated transition metal dichalcogenides (TMDs) of the form AxMC2, where A is a magnetic element of stoichiometry x between 0 and 1, M is a transition metal of stoichiometry 1, and C is a chalcogen of stoichiometry 2. Memory storage is achieved by fabricating these materials into crosses of two or more bars and driving DC current pulses along the bars to rotate the AFM order to a fixed angle with respect to the current pulse. Application of current pulses along different bars can switch the AFM order between multiple directions. Standard resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by the input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.
Analytis, James G.↗
GaN-based threshold switching device and memory diode
A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.
Fu, Kai↗
GaN-based threshold switching device and memory diode
A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.
Fu, Kai↗
Method of efficiently identifying rollback requests
Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allow a memory device to efficiently mark memory extents involved in an enhanced memory operation. An extent is marked if a meta state associated with the extent indicates that the extent is included in the enhanced memory operation. The largest memory extents of the operation are maintained in the memory device as a list of unmarked extents. When a primitive memory operation is received, the memory address is compared to the unmarked extents in the list to the meta state for that memory line. If the address is covered by the list of extents, or that line's meta state is marked, then the memory operation is performed including the enhanced memory operation.
Brewer, Tony M.↗