Development of the Circuit Design from the Logic Design of a Random Walk Machine Final Report
Logic design of small, high speed, random walk machine for solving Laplace equation
LOGIC CIRCUIT↗
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Results for “LOGICAL DESIGN”
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Computerized logic design of digital circuits
Procedure performs all work required for logic design of digital counters or sequential circuits and simplification of Boolean expressions. Program provides simple, accurate, and comprehensive logic design capability to users both experienced and totally inexperienced in logic design
Gussow, S.↗
Design guidelines for the testability of microprocessor based logic designs
This paper deals with the issue of designing microprocessor based systems with testability in mind. The ease of eventual testability should be a design consideration from the earliest design stage. Design guidelines with explicit examples for ease of testability are given. The issue of testing microprocessors as contrasted with testing random logic design is addressed, and procedures are delineated for the testability of microprocessors. Microprocessor testability design guidelines are discussed both at the design stage of the microprocessor itself as well as at the stage where the processor is imbedded as a component in a larger system. Specific instances and examples of a collection of design do's and don'ts are provided.
Mathur, F. P.↗
Logic Design Pathology and Space Flight Electronics
Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.
Katz, Richard↗
Computerized logic design of digital circuits
This manual presents a computer program that performs all the work required for the logic design of digital counters or sequential circuits and the simplification of Boolean logic expressions. The program provides both the experienced and inexperienced logic designer with a comprehensive logic design capability. The manual contains Boolean simplification and sequential design theory, detailed instructions for use of the program, a large number of illustrative design examples, and complete program documentation.
Sussow, S.↗
Logic Design Pathology and Space Flight Electronics
This presentation looks at logic design from early in the US Space Program, it examines faults in recent logic designs, and gives some examples from the analysis of new tools and techniques.
Katz, Richard B.↗
Logic Design Pathology and Space Flight Electronics
This paper presents a look at logic design from early in the US Space Program and examines faults in recent logic designs. Most examples are based on flight hardware failures and analysis of new tools and techniques. The paper is presented in viewgraph form.
Katz, Richard B.↗
Logical design techniques for error control.
Logical processing units and interconnection networks design noting reliability, fault diagnosis, computer coordination of data and control processes, etc
DATA CONTROL SYSTEM↗
Fail-Safe Logic Design Strategies Within Modern FPGA Architectures
Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.
Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
Quicklist: The basis for a computer aided logic design system
Quicklist, a preprocessor for an existing wire list program that cuts the description of the wire list by about 67 percent over previous methods, is described. Quicklist uses two different methods to shorten the input data. The first of these is the use of parentheses to allow a compact way of describing signal names which increment (or decrement) by one, i.e., typical signal names in a bus. The other method used is the equal sign. Using this symbol in a signal list says that the rest of the signals on that chip are the same as those on the previous chip described. Quicklist is intended to be the basis of a computer aided logic design system.
Lushbaugh, W. A.↗
Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures
Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.
Rickard, D. A.↗
Automated logical design of digital devices technical report no. 2
Explore the source record for details and available documents.
Carroll, C. C.↗
Logic design for dynamic and interactive recovery.
Recovery in a fault-tolerant computer means the continuation of system operation with data integrity after an error occurs. This paper delineates two parallel concepts embodied in the hardware and software functions required for recovery; detection, diagnosis, and reconfiguration for hardware, data integrity, checkpointing, and restart for the software. The hardware relies on the recovery variable set, checking circuits, and diagnostics, and the software relies on the recovery information set, audit, and reconstruct routines, to characterize the system state and assist in recovery when required. Of particular utility is a handware unit, the recovery control unit, which serves as an interface between error detection and software recovery programs in the supervisor and provides dynamic interactive recovery.
Carter, W. C.↗
Banning standard cell engineering notebook
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The information is presented in a form useful for systems designs, logic design, and the preparation of inputs to both sets of Design Automation programs for array design and analysis. A data sheet is provided for each cell and gives the cell name, the cell number, its logic symbol, Boolean equation, truth table, circuit schematic circuit composite, input-output capacitances, and revision date. The circuit type file, also given for each cell, together with the logic drawing contained on the data sheet provides all the information required to prepare input data files for the Design Automation Systems. A detailed description of the electrical design procedure is included.
Source record↗
Automatic flow chart design.
Logical structure of automatic flow chart design, describing element ordering and sorting
FLOW GRAPH↗
"Glitch Logic" and Applications to Computing and Information Security
This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.
hardware vulnerabilities↗
Flight Design System-1 System Design Document. Volume 9: Executive logic flow, program design language
The detailed logic flow for the Flight Design System Executive is presented. The system is designed to provide the hardware/software capability required for operational support of shuttle flight planning.
Source record↗
An architecture for designing fuzzy logic controllers using neural networks
Described here is an architecture for designing fuzzy controllers through a hierarchical process of control rule acquisition and by using special classes of neural network learning techniques. A new method for learning to refine a fuzzy logic controller is introduced. A reinforcement learning technique is used in conjunction with a multi-layer neural network model of a fuzzy controller. The model learns by updating its prediction of the plant's behavior and is related to the Sutton's Temporal Difference (TD) method. The method proposed here has the advantage of using the control knowledge of an experienced operator and fine-tuning it through the process of learning. The approach is applied to a cart-pole balancing system.
Berenji, Hamid R.↗