Quicklist: The basis for a computer aided logic design system

Abstract

Quicklist, a preprocessor for an existing wire list program that cuts the description of the wire list by about 67 percent over previous methods, is described. Quicklist uses two different methods to shorten the input data. The first of these is the use of parentheses to allow a compact way of describing signal names which increment (or decrement) by one, i.e., typical signal names in a bus. The other method used is the equal sign. Using this symbol in a signal list says that the rest of the signals on that chip are the same as those on the previous chip described. Quicklist is intended to be the basis of a computer aided logic design system.