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Field effect transistors with nonuniform doping profiles along channel, calculating carrier accumulation and space charge limited current flow by two dimensional model analysis
Neutron and gamma radiation effects on field effect transistor and injection transistors
An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.
Field effect transistors as direct current amplifiers
CADAT field-effect transistor simulator (FETSIM) analyzes dc and transient behavior of metal-oxide-semiconductor (MOS) circuits. Both N-MOS and P-MOS transistor configurations in either bulk of silicon-on-sapphire (SOS) technology and almost any combination of R/C elements are analyzed.
Metal oxide semiconductor field effect transistor circuit development and laminated electronic packaging for computer storage devices
Metal-Insulated-Semiconductor Field Effect Transistor /MISFET/ device uses a silicon nitride passivation layer over a thin silicon oxide layer to enhance the radiation tolerance. It is useful in electronic systems exposed to space radiation environment or the effects of nuclear weapons.
LF noise generation in junction field effect transistors due to charge fluctuations
Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.
Solid-state amplifier utilizes field effect transistors and planar junction diodes to provide a logarithmic response to a wide range of input signals.
Pseudomorphic In0.15Ga0.85As/A10.15Ga0.85As modulation-doped field effect transistors (MODFET's) exhibiting extremely good dc characteristics have been successfully fabricated. dc transconductance in these strained-layer structures of 270 mS/mm was measured for 1-micron gate, normally-on devices at 300 K. Maximum drain current levels are 290 mA/mm, with excellent pinch-off and saturation characteristics. The transconductance increased to 360 mS/mm at 77 K while no persistent photoconductivity or drain collapse was observed. Preliminary microwave results indicate a 300-K current gain cutoff frequency of about 20 GHz. These results are equivalent to the best GaAs/AlGaAs MODFET results and are due in part to the improved transport properties and carrier confinement in the InGaAs quantum well.
Field effect transistor devices comprising III-V semiconductors and organic gate dielectric materials, such dielectric materials as can afford flexibility in device design and fabrication.
Feasibility of fabricating thick film, insulated gate field effect transistor using integrated screened circuit technology
Small current measurements with insulated-gate field effect transistor electrometers
Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.
A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.
Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.
We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.