Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “GaTe”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 1,639 records · Page 91
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

1.0 to 2.5 micrometer short wavelength infrared /SWIR/ linear array technology for low background applications

A design concept is presented for a hybrid linear focal plane array operating in the 1.0 to 2.5 micron band under low background conditions such as encountered in spaceborne missions. The concept is based on direct gate coupling of the input from a photovoltaic mercury-cadmium telluride detector into a CCD multiplexer. Theoretical analysis indicates a specific detectivity at peak wavelength on the order of 10 to the 12th cm sq rt Hz/W when the system is operating at 200 K. Values of the voltage responsivity, specific detectivity and the relative voltage noise levels of the coupled system obtained in experimental studies with direct-gate-coupled 4.0-micron detectors support the theoretical analysis performed for the case of system detectivity limited by the CCD 1/f noise.

Stobie, J.↗
NASA NTRS1983

Logic Simulator Program

The source code for the SPICE 2 program was deblocked in order to isolate and compile the subroutine in an effort to provide a software simulation of discrete and combinatorial electronic components. Incompatibilities between the UNIVAC 1180 FORTRAN and the Sigma V CP-V FORTRAN 4 were resolved. The SPICE 2 model is to be used to determine gate and fan-out delays, logic state conditions, and signal race conditions for transistor array elements and circuit logic to be patterned in the (SPI) 7101 CMOS silicon gate semicustom array. The simulator is to be operable from the CP-V time sharing terminals.

Agarwal, R. K.↗
NASA NTRS1983

Techniques for avoiding discrimination errors in the dynamic sampling of condensable vapors

In the mass spectrometric sampling of dynamic systems, measurements of the relative concentrations of condensable and noncondensable vapors can be significantly distorted if some subtle, but important, instrumental factors are overlooked. Even with in situ measurements, the condensables are readily lost to the container walls, and the noncondensables can persist within the vacuum chamber and yield a disproportionately high output signal. Where single pulses of vapor are sampled this source of error is avoided by gating either the mass spectrometer ""on'' or the data acquisition instrumentation ""on'' only during the very brief time-window when the initial vapor cloud emanating directly from the vapor source passes through the ionizer. Instrumentation for these techniques is detailed and its effectiveness is demonstrated by comparing gated and nongated spectra obtained from the pulsed-laser vaporization of several materials.

Lincoln, K. A.↗
NASA NTRS1984

Upset susceptibility study employing circuit analysis and digital simulation

This paper describes an approach to predicting the susceptibility of digital systems to signal disturbances. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, Electromagnetic Interference (EMI) and Electromagnetic Pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload will bring the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The Super-Sceptre (system for circuit evaluation of transient radiation effects) Program was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

Carreno, V. A.↗
NASA NTRS1983

Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

Brucker, G. J.↗
NASA NTRS1983

Cooled grating infrared spectrometer for astronomical observations

A liquid helium-cooled infrared spectrometer for the 16 to 50 micron range is described. The instrument has six detectors, three each of Si:Sb and Ge:Ga and two diffraction gratings mounted back-to-back. Cold preoptics are used to match the spectrometer to the telescope. In its nominal configuration the system resolution is 0.03 micron from 16 to 30 microns and 0.07 micron from 28 to 50 microns. A cooled filter wheel is used to change order sorting filters. The gratings are driven by a steel band and gear train operating at 4 K. The detector outputs are amplified by a TIA, employing a matched pair of JFETs operating at 70 K inside the dewar. The external warm electronics include a gain stage for the TIA and dc-coupled gating circuit to remove charged-particle (cosmic-ray secondary)-induced noise spikes. The gating circuit reduces the overall system noise by a factor of two when the spectrometer is used on NASA's Kuiper Airborne Observatory. Sample spectra are presented and the deglitcher performance is illustrated.

Houck, J. R.↗
NASA NTRS1986

Efficient Power Amplifier for Motor Control

Pulse-width-modulated amplifier supplies high current as efficiently as low current needed for starting and running motor. Key to efficiency of motor-control amplifier is V-channel metal-oxide/semiconductor transistor Q1. Device has low saturation resistance. However, has large gate input capacitance and small margin between its turn-on voltage and maximum allowable gate-to-source voltage. Circuits for output stages overcome limitations of VMOS device.

Brown, R. J.↗
NASA NTRS1984

Upset susceptibility study employing circuit analysis and digital simulation

An approach to predict the susceptibility of digital systems to signal disturbances is described. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, electromagnetic interference (EMI), and electromagnetic pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload brings the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The super-sceptre (system for circuit evaluation of transient radiation effects) programs was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

Carreno, V. A.↗
NASA NTRS1985

Box truss development and its application

Since 1977, Martin Marietta Denver Aerospace has aggressively pursued development of deployable structural systems applicable to a wide variety of Shuttle-transportable large space system requirements. This effort has focused on the deployable box truss, mechanisms and materials development, mesh reflector design and fabrication, gate frame truss design and fabrication, and offset-fed antenna design and analysis. The activities discussed are: box truss design; metal matrix composites; precision joints; enhanced passive damping design; mesh reflector development; gate frame truss for solar arrays; 15-meter spinning radio meter; and 60 x 120 meter push broom antenna.

Coyner, J. V.↗
NASA NTRS1985

Advanced detectors and signal processing for bubble memories

The feasibility of combining silicon and magnetic bubble technologies is demonstrated. Results of bubble film annealing indicate that a low temperature silicon on garnet technology is the most likely one to succeed commercially. Annealing ambients are also shown to have a major effect on the magnetic properties of bubble films. Functional MOSFETs were fabricated on bubble films coated with thick (approximately 1 micron) SiO2 layers. The two main problems with these silicon on garnet MOSFETs are low electron mobilities and large gate leakage currents. Results indicate that the laser recrystallized silicon and gate oxide (SiO2) layers are contaminated. The data suggest that part of the contaminating ions originate in the sputtered oxide spacer layer and part originates in the bubble film itself. A diffusion barrier, such as silicon nitride, placed between the bubble film and the silicon layer should eliminate the contamination induced problem.

Kryder, M. H.↗
NASA NTRS1983

Leakage effects in n-GaAs MESFET with n-GaAs buffer layer

Whereas improvement of the interface between the active layer and the buffer layer has been demonstrated, the leakage effects can be important if the buffer layer resistivity is not sufficiently high and/or the buffer layer thickness is not sufficiently small. It was found that two buffer leakage currents exist from the channel under the gate to the source and from drain to the channel in addition to the buffer leakage resistance between drain and source. It is shown that for a 1 micron gate-length n-GaAs MESFET, if the buffer layer resistivity is 12 OHM-CM and the buffer layer thickness h is 2 microns, the performance of the device degrades drastically. It is suggested that h should be below 2 microns.

Wang, Y. C.↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS1983

New results in fault latency modelling

The test design and results from assessment of the performance of the self-test program and the extent of fault latency in a redundant flight control system (FCS) are reported. Assembly language programming generated gate-level faults directed to every avionics component. Details of the fault-simulation software are described, noting the input needed to match the five control-surface parameters managed by the FCS. Most faults were immediately detected, and component-level faults, occurring at pins, were more easily noted than gate-level faults. The results indicated that a 200-word self-test program is sufficient to obtain a fault coverage of 85 percent. Minor hardware changes are required to reach levels over 90 percent.

Mcgough, J. G.↗
NASA NTRS1986

Submicron Silicon MOSFET

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Daud, T.↗
NASA NTRS1986

Error propagation in a digital avionic processor: A simulation-based study

An experimental analysis to study error propagation from the gate to the chip level is described. The target system is the CPU in the Bendix BDX-930, an avionic miniprocessor. Error activity data for the study was collected via a gate-level simulation. A family of distributions to characterize the error propagation, both within the chip and at the pins, was then generated. Based on these distributions, measures of error propagation and severity were defined. The analysis quantifies the dependency of the measured error propagation on the location of the fault and the type of instruction/microinstruction executed.

Lomelino, D.↗
NASA NTRS1985

JFET reflection oscillator

A high frequency oscillator circuit is provided using a low cost junction type field effect transistor (T sub 1) with a tuned circuit connected to its gate. The frequency of operation is determined by the tuned circuit and the capacitance reflected from the source to the gate. The transistor is matched to the frequency of operation so that this frequency falls within the roll-off portion of the transistor's transconductance verses frequency curve, preferably somewhat above the 3 db point in frequency. Phase shift necessary to sustain oscillation occurs due to the operation of the transistor in the roll-off portion of the curve and the addition of a phase shifting network (R sub 1, C sub 1) at the source.

Kleinberg, L. L.↗
NASA NTRS1986

Overcash, D. R.

The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.

Source record↗
NASA NTRS1985

Double-injection, deep-impurity switch development

The overall objective of this program was the development of device design and process techniques for the fabrication of a double-injection, deep-impurity (DI) sup 2 silicon switch that operates in the 2-10 kV range with conduction current values of 5 A at 2 kV and 1 A at 10 kV. Other major specifications include a holding voltage of 10 V with no gate current, 10 microsec switching time, and power dissipation of 50 W at 75 C. It was decided to concentrate on the lateral circular devices in order to optimize the gold diffusion. This resulted in devices that are much better switches (approx.1 micro sec switching time), and in a gold diffusion process that is much more controllable than those previously developed. Some results with injection-gated devices were also obtained. The current conduction for V less than VT was analyzed and seen to agree, for the most part, with Lampert's theory. Various sections of this report describe the device designs, wafer-processing techniques, and various measurements which include ac and dc characteristics and four-point probe.

Whitson, D. W.↗