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Results for “semiconductor devices”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
NASA NTRS1978

Effects of ultrathin oxides in conducting MIS structures on GaAs

Schottky barrier-type GaAs baseline devices (semiconductor surface etched and then immediately metalized) and GaAs conducting metal oxide-semiconductor devices are fabricated and characterized. The baseline surfaces (no purposeful oxide) are prepared by a basic or an acidic etch, while the surface for the MIS devices are prepared by oxidizing after the etch step. The metallizations used are thin-film Au, Ag, Pd, and Al. It is shown that the introduction of purposeful oxide into these Schottky barrier-type structures examined on n-type GaAs modifies the barrier formation, and that thin interfacial layers can modify barrier formation through trapping and perhaps chemical reactions. For Au- and Pd-devices, enhanced photovoltaic performance of the MIS configuration is due to increased barrier height.

Childs, R. B.↗
DOE OSTI2022

Electrostatic harvester device

An electrostatic harvester device for charging an energy storage device is provided. The electrostatic harvester device comprises an inductor, a variable capacitor device, a semiconductor device, and a plurality of transistors. The inductor is operable to receive electric charge and store the electric charge. The variable capacitor device is configured to receive electric charge from the inductor and to change capacitance in response to physical stimulation. The semiconductor device is operable to allow electric current to flow from the variable capacitor device. The transistors are operable to connect at least two of the aforementioned devices. At least one of the transistors comprises at least one of gallium nitride or aluminum gallium nitride.

Wilson, Amy Charlene↗
NASA NTRS1980

JANTX2N3811 dual transistor

Report evaluates effects of power and temperature overstress on Motorola and National Semiconductor devices. National Semiconductor devices exceeded 50 percent failure after 160 hours at 225 deg C. Motorola suffered more rejects but failures occurred at 300 deg C. Difference in lead bonding technique may explain performance.

Source record↗
DOE OSTI2024

Thermal scanning probe and laser lithography for patterning nanowire based quantum devices

Semiconductor nanowire (NW) quantum devices offer a promising path for the pursuit and investigation of topologically-protected quantum states, and superconducting and spin-based qubits that can be controlled using electric fields. Theoretical investigations into the impact of disorder on the attainment of dependable topological states in semiconducting nanowires with large spin–orbit coupling and g-factor highlight the critical need for improvements in both growth processes and nanofabrication techniques. In this work, we used a hybrid lithography tool for both the high-resolution thermal scanning probe lithography and high-throughput direct laser writing of quantum devices based on thin InSb nanowires with contact spacing of 200 nm. Electrical characterization demonstrates quasi-ballistic transport. The methodology outlined in this study has the potential to reduce the impact of disorder caused by fabrication processes in quantum devices based on 1D semiconductors.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

42 ENGINEERING↗
NASA NTRS1985

Laser activated MTOS microwave device

A light-activated semiconductor device usable as an optoelectronic switch, pulse generator or optical detector is provided. A semiconductor device is disclosed which provides back-to-back metal-thin oxide-silicon (MTOS) capacitors. Each capacitor includes a thin, light-absorptive aluminum electrode which overlies a thin oxide layer and a lightly doped region implanted in an intrinsic silicon substrate.

Maserjian, J.↗
NASA NTRS1996

Silicon Carbide High-Temperature Power Rectifiers Fabricated and Characterized

The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. Silicon carbide's demonstrated ability to function under extreme high-temperature, high power, and/or high-radiation conditions will enable significant improvements to a far ranging variety of applications and systems. These improvements range from improved high-voltage switching for energy savings in public electric power distribution and electric vehicles, to more powerful microwave electronics for radar and cellular communications, to sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. In the case of jet engines, uncooled operation of 300 to 600 C SiC power actuator electronics mounted in key high-temperature areas would greatly enhance system performance and reliability. Because silicon cannot function at these elevated temperatures, the semiconductor device circuit components must be made of SiC. Lewis' HTIES group recently fabricated and characterized high-temperature SiC rectifier diodes whose record-breaking characteristics represent significant progress toward the realization of advanced high-temperature actuator control circuits. The first figure illustrates the 600 C probe-testing of a Lewis SiC pn-junction rectifier diode sitting on top of a glowing red-hot heating element. The second figure shows the current-versus voltage rectifying characteristics recorded at 600 C. At this high temperature, the diodes were able to "turn-on" to conduct 4 A of current when forward biased, and yet block the flow of current ($quot;turn-off") when reverse biases as high as 150 V were applied. This device represents a new record for semiconductor device operation, in that no previous semiconductor electronic device has ever simultaneously demonstrated 600 C functionality, and 4-A turn-on and 150-V rectification. The high operating current was achieved despite severe device size limitations imposed by present-day SiC wafer defect densities. Further substantial increases in device performance can be expected when SiC wafer defect densities decrease as SiC wafer production technology matures.

Source record↗
NASA NTRS1977

Semiconductor ohmic contact

A semiconductor device has one surface of P type conductivity material having a wide energy bandgap and a large crystal lattice parameter. Applied to the P type surface of the semiconductor device is a degenerate region of semiconductor material, preferably a group III-V semiconductor material, having a narrower energy bandgap. The degenerate region is doped with tin to increase the crystal lattice of the region to more closely approximate the crystal lattice of the one surface of the semiconductor device. The degenerate region is compensatingly doped with a P type conductivity modifier. An electrical contact is applied to one surface of the degenerate region forming an ohmic contact with the semiconductor device.

Hawrylo, Frank Zygmunt↗
DOE OSTI2024

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into “Beyond CMOS” and “More than Moore” paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. Finally, the outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

36 MATERIALS SCIENCE↗