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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Si/SiGe QuBus for single electron information-processing devices with memory and micron-scale connectivity function

The connectivity within single carrier information-processing devices requires transport and storage of single charge quanta. Single electrons have been adiabatically transported while confined to a moving quantum dot in short, all-electrical Si/SiGe shuttle device, called quantum bus (QuBus). Here we show a QuBus spanning a length of 10 μm and operated by only six simply-tunable voltage pulses. We introduce a characterization method, called shuttle-tomography, to benchmark the potential imperfections and local shuttle-fidelity of the QuBus. The fidelity of the single-electron shuttle across the full device and back (a total distance of 19 μm) is (99.7 ± 0.3) %. Using the QuBus, we position and detect up to 34 electrons and initialize a register of 34 quantum dots with arbitrarily chosen patterns of zero and single-electrons. The simple operation signals, compatibility with industry fabrication and low spin-environment-interaction in 28 Si/SiGe, promises long-range spin-conserving transport of spin qubits for quantum connectivity in quantum computing architectures.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

GPU Direct I/O with HDF5

Exascale HPC systems are being designed with accelerators, such as GPUs, to accelerate parts of applications. In machine learning workloads as well as large-scale simulations that use GPUs as accelerators, the CPU (or host) memory is currently used as a buffer for data transfers between GPU (or device) memory and the file system. If the CPU does not need to operate on the data, then this is sub-optimal because it wastes host memory by reserving space for duplicated data. Furthermore, this “bounce buffer” approach wastes CPU cycles spent on transferring data. A new technique, NVIDIA GPUDirect Storage (GDS), can eliminate the need to use the host memory as a bounce buffer. Thereby, it becomes possible to transfer data directly between the device memory and the file system. This direct data path shortens latency by omitting the extra copy and enables higher-bandwidth. To take full advantage of GDS in existing applications, it is necessary to provide support with existing I/O libraries, such as HDF5 and MPI-IO, which are heavily used in applications. In this paper, we describe our effort of integrating GDS with HDF5, the top I/O library at NERSC and at DOE leadership computing facilities. We design and implement this integration using a HDF5 Virtual File Driver (VFD). The GDS VFD provides a file system abstraction to the application that allows HDF5 applications to perform I/O without the need to move data between CPUs and GPUs explicitly. We compare performance of the HDF5 GDS VFD with explicit data movement approaches and demonstrate superior performance with the GDS method.

Ravi, J↗
DOE OSTI2018

Meta Allocator

Metall provides simplified memory allocation interfaces for out-of-core applications that use block-addressable persistent memory devices to extend the capacity of main memory and to persistently store data on such devices. Using Metall, users can dynamically allocate memory in persistent memory devices just as in main-memory. In order to store data persistently and reload the data easily, Metall also provides a key-value store like interface. Metall offers APIs to allocate contiguous memory regions like malloc(3) does and to construct C++ objects, including STL-like containers. Metall has a similar APIs to Boost.Interprocess (BIP).

Iwabuchi, Keita↗
DOE OSTI2018

The OpenACC data model: Preliminary study on its major challenges and implementations

This paper describes how the OpenACC data model is implemented in current OpenACC compilers, ranging from research compilers (OpenUH and OpenARC) to a commercial compiler (the PGI OpenACC compiler). First, we summarize various memory architectures in today’s accelerator systems. We then describe details and issues in implementing the OpenACC data model in three different OpenACC compilers. This includes managing page tables, asynchronous data transfers, asynchronous memory allocate and free, host data construct, aliasing on a data directive, reusing device memory, partially present data, and adjacent data. We also discusses ongoing work to manage large, complex dynamic data structures. We measured the present table lookups, device memory allocation, pinned memory allocation, and managed memory in the three OpenACC compilers using eight OpenACC applications (seven from the SPEC ACCEL benchmark suite and a shock-hydrodynamics mini-application called LULESH).

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Computing rank‐revealing factorizations of matrices stored out‐of‐core

This paper describes efficient algorithms for computing rank-revealing factorizations of matrices that are too large to fit in main memory (RAM), and must instead be stored on slow external memory devices such as disks (out-of-core or out-of-memory). Traditional algorithms for computing rank-revealing factorizations (such as the column pivoted QR factorization and the singular value decomposition) are very communication intensive as they require many vector-vector and matrix-vector operations, which become prohibitively expensive when data is not in RAM. Randomization allows to reformulate new methods so that large contiguous blocks of the matrix are processed in bulk. The paper describes two distinct methods. The first is a blocked version of column pivoted Householder QR, organized as a “left-looking” method to minimize the number of the expensive write operations. The second method results employs a UTV factorization. It is organized as an algorithm-by-blocks to overlap computations and I/O operations. As it incorporates power iterations, it is much better at revealing the numerical rank. Numerical experiments on several computers demonstrate that the new algorithms are almost as fast when processing data stored on slow memory devices as traditional algorithms are for data stored in RAM.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Collective memory transfer devices and methods for multiple-core processors

This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2007

Ion-Conducting Organic/Inorganic Polymers

Ion-conducting polymers that are hybrids of organic and inorganic moieties and that are suitable for forming into solid-electrolyte membranes have been invented in an effort to improve upon the polymeric materials that have been used previously for such membranes. Examples of the prior materials include perfluorosulfonic acid-based formulations, polybenzimidazoles, sulfonated polyetherketone, sulfonated naphthalenic polyimides, and polyethylene oxide (PEO)-based formulations. Relative to the prior materials, the polymers of the present invention offer greater dimensional stability, greater ease of formation into mechanically resilient films, and acceptably high ionic conductivities over wider temperature ranges. Devices in which films made of these ion-conducting organic/inorganic polymers could be used include fuel cells, lithium batteries, chemical sensors, electrochemical capacitors, electrochromic windows and display devices, and analog memory devices. The synthesis of a polymer of this type (see Figure 1) starts with a reaction between an epoxide-functionalized alkoxysilane and a diamine. The product of this reaction is polymerized by hydrolysis and condensation of the alkoxysilane group, producing a molecular network that contains both organic and inorganic (silica) links. The silica in the network contributes to the ionic conductivity and to the desired thermal and mechanical properties. Examples of other diamines that have been used in the reaction sequence of Figure 1 are shown in Figure 2. One can use any of these diamines or any combination of them in proportions chosen to impart desired properties to the finished product. Alternatively or in addition, one could similarly vary the functionality of the alkoxysilane to obtain desired properties. The variety of available alkoxysilanes and diamines thus affords flexibility to optimize the organic/inorganic polymer for a given application.

Kinder, James D.↗
DOE OSTI2015

Store operation with conditional push of a tag value to a queue

According to one embodiment, a method for a store operation with a conditional push of a tag value to a queue is provided. The method includes configuring a queue that is accessible by an application, setting a value at an address in a memory device including a memory and a controller, receiving a request for an operation using the value at the address and performing the operation. The method also includes the controller writing a result of the operation to the address, thus changing the value at the address, the controller determining if the result of the operation meets a condition and the controller pushing a tag value to the queue based on the condition being met, where the tag value in the queue indicates to the application that the condition is met.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Memory instruction for memory tiers

Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.

Roberts, David Andrew↗
DOE OSTI2015

Direct observation of conductive filament formation in Alq3 based organic resistive memories

This work explores resistive switching mechanisms in non-volatile organic memory devices based on tris(8-hydroxyquinolie)aluminum (Alq{sub 3}). Advanced characterization tools are applied to investigate metal diffusion in ITO/Alq{sub 3}/Ag memory device stacks leading to conductive filament formation. The morphology of Alq{sub 3}/Ag layers as a function of the metal evaporation conditions is studied by X-ray reflectivity, while depth profile analysis with X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry is applied to characterize operational memory elements displaying reliable bistable current-voltage characteristics. 3D images of the distribution of silver inside the organic layer clearly point towards the existence of conductive filaments and allow for the identification of the initial filament formation and inactivation mechanisms during switching of the device. Initial filament formation is suggested to be driven by field assisted diffusion of silver from abundant structures formed during the top electrode evaporation, whereas thermochemical effects lead to local filament inactivation.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Cache coherence for processing in memory

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO{sub 2} gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2014

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Differential emissivity based evaporable particle measurement

A differential emissivity imaging device for measuring evaporable particle properties can include a heated plate, a thermal camera, a memory device, and an output interface. The heated plate can have an upper surface oriented to receive falling evaporable particles. The evaporable particles have a particle emissivity and the upper surface has a plate surface emissivity. The thermal camera can be oriented to produce a thermal image of the upper surface. A memory device can include instructions that cause the imaging device to calculate a mass of the individual evaporable particle via heat conduction using a calculated surface area and an evaporation time.

Garrett, Tim↗
DOE OSTI2012

Formation of SiGe nanocrystals embedded in Al{sub 2}O{sub 3} for the application of write-once-read-many-times memory

The structure of SiGe nanocrystals embedded in Al{sub 2}O{sub 3} formed by sequential deposition of Al{sub 2}O{sub 3}/Si/Ge/Al{sub 2}O{sub 3} and a subsequent annealing was confirmed by transmission electron microscopy and energy dispersive spectroscopy (EDS), and its application for write-once-read-many-times (WORM) memory devices was explored in this study. By applying a -10 V pulse for 1 s, a large amount of holes injected from Si substrate are stored in the nanocrystals and consequently, the current at +1.5 V increases by a factor of 10{sup 4} as compared to that of the initial state. Even with a smaller -5 V pulse for 1 {mu}s, a sufficiently large current ratio of 36 can still be obtained, verifying the low power operation. Since holes are stored in nanocrystals which are isolated from Si substrate by Al{sub 2}O{sub 3} with good integrity and correspond to a large valence band offset with respect to Al{sub 2}O{sub 3}, desirable read endurance up to 10{sup 5} cycles and excellent retention over 100 yr are achieved. Combining these promising characteristics, WORM memory devices are appropriate for high-performance archival storage applications.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Self-consistent modelling of electrochemical strain microscopy in mixed ionic-electronic conductors: Nonlinear and dynamic regimes

The frequency dependent Electrochemical Strain Microscopy (ESM) response of mixed ionic-electronic conductors is analyzed within the framework of Fermi-Dirac statistics and the Vegard law, accounting for steric effects from mobile donors. The emergence of dynamic charge waves and nonlinear deformation of the surface in response to bias applied to the tip-surface junction is numerically explored. The 2D maps of the strain and concentration distributions across the mixed ionic-electronic conductor and bias-induced surface displacements are calculated. The obtained numerical results can be applied to quantify the ESM response of Li-based solid electrolytes, materials with resistive switching, and electroactive ferroelectric polymers, which are of potential interest for flexible and high-density non-volatile memory devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1992

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

Thin film ferroelectric capacitors comprising a ferroelectric film sandwiched between electrodes for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode. The anneal is done so as to form the interface between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550 to 600 C for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the nonswitching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the nonswitching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Thakoor, Sarita↗
NASA NTRS1994

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

Thin film ferroelectric capacitors (10) comprising a ferroelectric film (18) sandwiched between electrodes (16 and 20) for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode (20). The anneal is done so as to form the interface (22) between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550.degree. to 600.degree. C. for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the non-switching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the non-switching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Thakoor, Sarita↗