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At least 163 records · Page 9

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NASA NTRS1983

Latchup in CMOS devices from heavy ions

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Soliman, K.↗

NASA NTRS1985

Latchup in CMOS Integrated Circuits

Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.

Soliman, K. A.↗

NASA NTRS1983

Development of a radiation-hard CMOS process

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Power, W. L.↗

NASA NTRS1985

Hardening of commercial CMOS PROMs with polysilicon fusible links

The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

Newman, W. H.↗

NASA NTRS1986

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Olson, E. M.↗

NASA NTRS1987

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Zoutendyk, J. A.↗

NASA NTRS1987

CMOS detector cells for holographic optical interconnects in microcircuits

This paper reports on the characterization of CMOS detectors for holographic optical interconnects in micro circuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate the identification of the sample area under investigation. An isolated photodiode and load circuit has been characterized to determine responsivity, response time, and light spot positioning effects. The threshold of optical gate cells incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 microW light input. Threshold power was 0.5 microW light input.

Wu, W. H.↗

NASA NTRS1988

A CMOS matrix for extracting MOSFET parameters before and after irradiation

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Blaes, B. R.↗

NASA NTRS1990

Upper-Bound Estimates Of SEU in CMOS

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Edmonds, Larry D.↗

NASA NTRS1990

Effects Of Dose Rates On Radiation Damage In CMOS Parts

Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

Goben, Charles A.↗

NASA NTRS1990

Failures Of CMOS Devices At Low Radiation-Dose Rates

Method for obtaining approximate failure-versus-dose-rate curves derived from experiments on failures of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated circuits irradiated by Co60 and Cs137 radioactive sources.

Goben, Charles A.↗

NASA NTRS1989

A quasi-passive CMOS pipeline D/A converter

A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.

Wang, Fong-Jim↗

NASA NTRS1989

Variation in SEU sensitivity of dose-imprinted CMOS SRAMs

The authors report on an experimental study of dose-induced changes in SEU (single-event-upset) sensitivity of CMOS static RAMs. Two time regimes were investigated following exposure of memories to cobalt-60 gamma rays: the near term, within a few hours after exposure, and the long term, after many days. Samples were irradiated both at room and at liquid nitrogen temperatures. The latter procedure was used in order to freeze in the damage state until SEU measurements could be made prior to annealing. Results show that memories damaged by dose are more sensitive to upsets by heavy ions. The induced changes are substantial: threshold linear energy transfer (LET) values decreased by as much as 46 percent and asymptotic cross sections increased by factors of two to four (unannealed samples).

Stassinopoulos, E. G.↗

NASA NTRS1989

Read disturb errors in a CMOS static RAM chip

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Wood, Steven H.↗

NASA NTRS1990

End-of-fabrication CMOS process monitor

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Buehler, M. G.↗

NASA NTRS1991

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Blaes, B. R.↗

NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗

NASA NTRS1992

Low power SEU immune CMOS memory circuits

The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

Liu, M. N.↗