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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

Stabilizing Semiconductor Devices With Hydrogen

Damage by radiation healed rapidly. Feature provides continuous, rapid recovery of devices from degradation caused by hot electrons, photons, and ionizing radiation. Several candidate sites for palladium film catalysts, inserted during manufacture as integral parts of devices. Paladium films made by evaporation, sputtering, or chemical-vapor deposition. If additional storage required, thick layer of palladium plated on inside of package surrounding device. Hydrogen stored by exposing palladium to hydrogen gas just before package sealed hermetically.

Overhauser, Albert W.↗
NASA NTRS1988

Linear response theory for annealing of radiation damage in semiconductor devices

A theoretical study of the radiation/annealing response of MOS ICs is described. Although many experiments have been performed in this field, no comprehensive theory dealing with radiation/annealing response has been proposed. Many attempts have been made to apply linear response theory, but no theoretical foundation has been presented. The linear response theory outlined here is capable of describing a broad area of radiation/annealing response phenomena in MOS ICs, in particular, both simultaneous irradiation and annealing, as well as short- and long-term annealing, including the case when annealing is nearing completion. For the first time, a simple procedure is devised to determine the response function from experimental radiation/annealing data. In addition, this procedure enables us to study the effect of variable temperature and dose rate, effects which are of interest in spaceflight. In the past, the shift in threshold potential due to radiation/annealing has usually been assumed to depend on one variable: the time lapse between an impulse dose and the time of observation. While such a suggestion of uniformity in time is certainly true for a broad range of radiation annealing phenomena, it may not hold for some ranges of the variables of interest (temperature, dose rate, etc.). A response function is projected which is dependent on two variables: the time of observation and the time of the impulse dose. This dependence on two variables allows us to extend the theory to the treatment of a variable dose rate. Finally, the linear theory is generalized to the case in which the response is nonlinear with impulse dose, but is proportional to some impulse function of dose. A method to determine both the impulse and response functions is presented.

Litovchenko, Vitaly↗
NASA NTRS1988

Heavy ion induced Single Event Phenomena (SEP) data for semiconductor devices from engineering testing

The accumulation of JPL data on Single Event Phenomena (SEP), from 1979 to August 1986, is presented in full report format. It is expected that every two years a supplement report will be issued for the follow-on period. This data for 135 devices expands on the abbreviated test data presented as part of Refs. (1) and (3) by including figures of Single Event Upset (SEU) cross sections as a function of beam Linear Energy Transfer (LET) when available. It also includes some of the data complied in the JPL computer in RADATA and the SPACERAD data bank. This volume encompasses bipolar and MOS (CMOS and MHNOS) device data as two broad categories for both upsets (bit-flips) and latchup. It also includes comments on less well known phenomena, such as transient upsets and permanent damage modes.

Nichols, Donald K.↗
NASA NTRS1990

Silicon carbide semiconductor device fabrication and characterization

A number of basic building blocks i.e., rectifying and ohmic contacts, implanted junctions, MOS capacitors, pnpn diodes and devices, such as, MESFETs on both alpha and beta SiC films were fabricated and characterized. Gold forms a rectifying contact on beta SiC. Since Au contacts degrade at high temperatures, these are not considered to be suitable for high temperature device applications. However, it was possible to utilize Au contact diodes for electrically characterizing SiC films. Preliminary work indicates that sputtered Pt or Pt/Si contacts on beta SiC films are someways superior to Au contacts. Sputtered Pt layers on alpha SiC films form excellent rectifying contacts, whereas Ni layers following anneal at approximately 1050 C provide an ohmic contact. It has demonstrated that ion implantation of Al in substrates held at 550 C can be successfully employed for the fabrication of rectifying junction diodes. Feasibility of fabricating pnpn diodes and platinum gated MESFETs on alpha SiC films was also demonstrated.

Davis, R. F.↗
NASA NTRS1991

Advances in silicon carbide Chemical Vapor Deposition (CVD) for semiconductor device fabrication

Improved SiC chemical vapor deposition films of both 3C and 6H polytypes were grown on vicinal (0001) 6H-SiC wafers cut from single-crystal boules. These films were produced from silane and propane in hydrogen at one atmosphere at a temperature of 1725 K. Among the more important factors which affected the structure and morphology of the grown films were the tilt angle of the substrate, the polarity of the growth surface, and the pregrowth surface treatment of the substrate. With proper pregrowth surface treatment, 6H films were grown on 6H substrates with tilt angles as small as 0.1 degrees. In addition, 3C could be induced to grow within selected regions on a 6H substrate. The polarity of the substrate was a large factor in the incorporation of dopants during epitaxial growth. A new growth model is discussed which explains the control of SiC polytype in epitaxial growth on vicinal (0001) SiC substrates.

Powell, J. Anthony↗
NASA NTRS1991

Energy Models for One-Carrier Transport in Semiconductor Devices

Moment models of carrier transport, derived from the Boltzmann equation, made possible the simulation of certain key effects through such realistic assumptions as energy dependent mobility functions. This type of global dependence permits the observation of velocity overshoot in the vicinity of device junctions, not discerned via classical drift-diffusion models, which are primarily local in nature. It was found that a critical role is played in the hydrodynamic model by the heat conduction term. When ignored, the overshoot is inappropriately damped. When the standard choice of the Wiedemann-Franz law is made for the conductivity, spurious overshoot is observed. Agreement with Monte-Carlo simulation in this regime required empirical modification of this law, or nonstandard choices. Simulations of the hydrodynamic model in one and two dimensions, as well as simulations of a newly developed energy model, the RT model, are presented. The RT model, intermediate between the hydrodynamic and drift-diffusion model, was developed to eliminate the parabolic energy band and Maxwellian distribution assumptions, and to reduce the spurious overshoot with physically consistent assumptions. The algorithms employed for both models are the essentially non-oscillatory shock capturing algorithms. Some mathematical results are presented and contrasted with the highly developed state of the drift-diffusion model.

Jerome, Joseph W.↗
NASA NTRS1993

Method for anisotropic etching in the manufacture of semiconductor devices

Hydrocarbon polymer coatings used in microelectronic manufacturing processes are anisotropically etched by hyperthermal atomic oxygen beams (translational energies of 0.2 to 20 eV, preferably 1 to 10 eV). Etching with hyperthermal oxygen atom species obtains highly anisotropic etching with sharp boundaries between etched and mask protected areas.

Koontz, Steven L.↗
NASA NTRS1994

Characteristics of III-V Semiconductor Devices at High Temperature

This paper presents the development of III-V based pseudomorphic high electron mobility transistors (PHEMT's) designed to operate over the temperature range 77 to 473 K (-196 to 200 C). These devices have a pseudomorphic undoped InGaAs channel that is sandwiched between an AlGaAs spacer and a buffer layer; gate widths of 200, 400, 1600, and 3200 micrometers; and a gate length of 2 micrometers. Measurements were performed at both room temperature and 473 K (200 C) and show that the drain current decreases by 30 percent and the gate current increases to about 9 microns A (at a reverse bias of -1.5 V) at the higher temperature. These devices have a maximum DC power dissipation of about 4.5 W and a breakdown voltage of about 16 V.

Simons, Rainee N.↗
NASA NTRS1998

Predictive Models for Semiconductor Device Design and Processing

The device feature size continues to be on a downward trend with a simultaneous upward trend in wafer size to 300 mm. Predictive models are needed more than ever before for this reason. At NASA Ames, a Device and Process Modeling effort has been initiated recently with a view to address these issues. Our activities cover sub-micron device physics, process and equipment modeling, computational chemistry and material science. This talk would outline these efforts and emphasize the interaction among various components. The device physics component is largely based on integrating quantum effects into device simulators. We have two parallel efforts, one based on a quantum mechanics approach and the second, a semiclassical hydrodynamics approach with quantum correction terms. Under the first approach, three different quantum simulators are being developed and compared: a nonequlibrium Green's function (NEGF) approach, Wigner function approach, and a density matrix approach. In this talk, results using various codes will be presented. Our process modeling work focuses primarily on epitaxy and etching using first-principles models coupling reactor level and wafer level features. For the latter, we are using a novel approach based on Level Set theory. Sample results from this effort will also be presented.

Meyyappan, Meyya↗
NASA NTRS1979

Heterojunction semiconductor device

A layer of germanium on a body of P type conductivity single crystal indium phosphide provides a blocking heterojunction. This device will emit light when a suitable voltage is placed thereacross or the device can be used as a photoconductor to generate electrons when light is directed thereon.

Harwylo, Frank Z.↗
NASA NTRS1996

Porous silicon carbide (SIC) semiconductor device

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Shor, Joseph S.↗
NASA NTRS1987

Method of making a semiconductor device

There is disclosed herein a method of making a device made up of at least two separate parts each of which is formed of a patterned array with the parts being mounted one on the other, with the patterned arrays of the parts being aligned, such as a CCD imager having a color filter thereon. The two parts are made on separate substrates with a first alignment key being formed on each substrate. The first alignment keys are formed by photolithography using the same mask to form the first alignment keys on each substrate. The various features of each of the parts are then formed on each substrate with each feature being formed by a photolithographic step using a mask which is aligned to a first alignment key so as to align all the features. A second alignment key is formed on each substrate and is positioned on each substrate in the same relationship with a first alignment key. The second alignment keys are of a material and construction so as to be visible when radiation of a desired wavelength is directed through the substrates. A part formed on one of the substrates is placed over a part formed on the other substrate. Radiation is directed through the substrates and the second alignment keys are aligned so as to align the patterned array of the two parts.

Elabd, Hammam↗
NASA NTRS1988

High conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗
NASA NTRS1988

Method of making a high conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗
NASA NTRS2010

Accelerated Aging System for Prognostics of Power Semiconductor Devices

Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is based on actual conditions and it is fundamental for the prediction of RUL under anticipated future usage. Failure of electronic devices is of great concern as future aircraft will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. Therefore, development of prognostics solutions for electronics is of key importance. This paper presents an accelerated aging system for gate-controlled power transistors. This system allows for the understanding of the effects of failure mechanisms, and the identification of leading indicators of failure which are essential in the development of physics-based degradation models and RUL prediction. In particular, this system isolates electrical overstress from thermal overstress. Also, this system allows for a precise control of internal temperatures, enabling the exploration of intrinsic failure mechanisms not related to the device packaging. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only, avoiding the generation of thermal cycles. The temperature is controlled by active thermal-electric units. Several electrical and thermal signals are measured in-situ and recorded for further analysis in the identification of leading indicators of failures. This system, therefore, provides a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide a health management solution for electronic devices.

Celaya, Jose R.↗
NASA NTRS2012

The Effects of Thermal Cycling on Gallium Nitride and Silicon Carbide Semiconductor Devices for Aerospace Use

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These Include radiation, extreme temperatures, thermal cycling, to name a few. Preliminary data obtained on new Gallium Nitride and Silicon Carbide power devices under exposure to radiation followed by long term thermal cycling are presented. This work was done in collaboration with GSFC and JPL in support of the NASA Electronic Parts and Packaging (NEPP) Program

Patterson, Richard L.↗