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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Characterization of Digital Silicon Photomultipliers
Digital Silicon photomultipliers (Digital SiPMs) have become an increasingly viable option for single-photon detection due to their compact size and precise timing and resolution. The following work characterizes the noise performance of a diSiPM designed and tested in-house at Fermilab. The SiPM consists of a 26x32 array of single-photon avalanche diode (SPAD) cells. Through the implementation of a shift register masking circuit, individual SPAD cells can be enabled and disabled at will, allowing for precise detection measurements of single columns (accumulator channels) and cells. The provided circuit design operates on voltage clock pulses and collects data on clock edges allowing for precise tuning of the data collection process by varying the clock frequency, pulse width, and integration period.
First measurements with the CMS DAQ and Timing Hub prototype-1
The DAQ and Timing Hub is an ATCA hub board designed for the Phase-2 upgrade of the CMS experiment. In addition to providing high-speed Ethernet connectivity to all back-end boards, it forms the bridge between the sub-detector electronics and the central DAQ, timing, and trigger control systems. One important requirement is the distribution of several high-precision, phase-stable, and LHC synchronous clock signals for use by the timing detectors. The current paper presents first measurements performed on the initial prototype, with a focus on clock quality. It is demonstrated that the current design provides adequate clock quality to satisfy the requirements of the Phase-2 CMS timing detectors.
Symmetry Breaking in an Extended-O(2) Model
Motivated by attempts to quantum simulate lattice models with continuous Abelian symmetries using discrete approximations, we consider an extended-O(2) model that differs from the ordinary O(2) model by an explicit symmetry breaking term. Its coupling allows to smoothly interpolate between the O(2) model (zero coupling) and a $q$-state clock model (infinite coupling). In the latter case, a $q$-state clock model can also be defined for non-integer values of $q$. Thus, such a limit can also be considered as an analytic continuation of an ordinary $q$-state clock model to non-integer $q$. The phase diagram of the extended-O(2) model in the infinite coupling limit was established in our previous work, where it was shown that for non-integer $q$, there is a second-order phase transition at low temperature and a crossover at high temperature. In this work, we investigate the model at finite values of the coupling using Monte Carlo and tensor methods. The results may be relevant for configurable Rydberg-atom arrays.
Dynamic variable precision computation
A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.
Register-Like Block RAM: Implementation, Testing in FPGA and Applications for High Energy Physics Trigger Systems
In high energy physics experiment trigger systems, block memories are utilized for various purposes, especially in indexed searching algorithms. It is often demanded to globally reset all memory locations between different events which is a feature not supported in regular block memories. Another common demand is to be able to update the contents in any memory location in a single clock cycle. These two demands can be fulfilled with registers but the cost of using registers for large memory is unaffordable. In this paper, a register-like block memory design scheme is described, which allows updating memory locations in single clock cycle and effectively refreshing entire memory within a single clock. The implementation and test results are presented.
Aquatic organism tracking devices, systems and associated methods
Aquatic organism tracking devices, systems and associated methods are described. According to one aspect, an aquatic organism tracking device includes a housing, a transducer coupled with the housing and configured to transmit a data transmission externally of the housing and an aquatic organism associated with the tracking device, a programmable oscillator coupled with the housing, and wherein the programmable oscillator is configured to generate a clock signal having a selected one of a plurality of different frequencies, processing circuitry coupled with the housing and configured to receive the clock signal from the programmable oscillator and to execute a plurality of executable instructions according to the clock signal, a power source coupled with the housing and configured to store electrical energy, and wherein the processing circuitry is configured to control the provision of the electrical energy from the power source to the transducer to generate the data transmission as a result of the execution of the instructions.
The Tiny Triplet Finder as a Versatile Track Segment Seeding Engine for Trigger Systems
In high energy physics experiment trigger systems, track segment seeding is a resource consuming function and the primary reason is the computing complexity of the segment finding process. As the Moore's Law is reaching its physical limit, reducing computing complexity should be carefully considered, rather than keep piling up silicon resources. The Tiny Triplet Finder is a scheme that reduces the computing complexity of the segment seeding. As a proof of concept, a 3D track segment seeding engine core based on the Tiny Triplet Finder has been implemented and tested in a low-cost FPGA device. The seeding engine is designed to preselect and group hits (stubs) from detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hough transform space for r-z view and a Tiny Triplet Finder for r-phi view to implement 3D constraints. The seeding engine is organized as a pipeline so that each hit is processed in a single clock cycle. Taking advantage of the register-like storage block scheme which enables effectively resetting of a block RAM within a single clock cycle, clearing or refreshing the seeding engine takes only one clock cycles between two events. The Tiny Triplet Finder is also a generic coincidence finding scheme that can be used for many tasks. As a versatility demonstration, track segment finding performances for two distinctive detector geometries are tested in our seeding engine. In a collider barrel-layer geometry, the fake segment rates are studied for 3D (i.e., both r-phi and r-z views) and 2D (i.e., r-phi or r-z view only) configurations for high hit multiplicity events (>4000 hits/layer in the barrel region). Another detector geometry contains strip plane layers with timing information. The numbers of coincidences, both real or fake, with or without timing ("3D" or "2D") information at various hit multiplicities are studied.
Delay-locked-loop timing error mitigation
Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.
High-bandwidth reconfigurable data acquisition card
A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.
Characterization of Spurious Charge in SENSEI Skipper-CCDs
Skipper Charge-Coupled Devices (Skipper-CCDs) are a leading technology in the search for sub-GeV dark matter and coherent elastic neutrino-nucleus scattering. A key background for rare-event searches with these detectors arises from "spurious charge" -- single-electron events generated when charges are transferred through the active region to the serial register, and across the serial register to the readout stage. We present a characterization of spurious charge in both the active region and the serial register of SENSEI Skipper-CCDs, and show that, in a well-shielded low-background environment, the dominant contribution originates in the serial register during Skipper readout, when horizontal clocks are held at constant voltage between pixel transfers. Motivated by this finding, we develop a "tri-level" clocking scheme in which the held-low phase is raised to an intermediate voltage during readout to suppress trap-mediated charge generation. Using the SENSEI detector near the MINOS cavern, we measure a serial-register single-electron density of $(2.9 \pm 0.1) \times 10^{-5}$ electrons/pixel/image under standard SENSEI readout conditions, reduced to $(4.0 \pm 0.4) \times 10^{-6}$ electrons/pixel/image with tri-level clocking -- a factor of $\sim$7 improvement. This technique offers a promising path to lower backgrounds in current and future Skipper-CCD experiments.
Spin Squeezing with Itinerant Magnetic Dipoles
Entanglement can improve the measurement precision of quantum sensors beyond the shot noise limit. Neutral atoms, the basis of some of the most precise and accurate optical clocks and interferometers, do not naturally exhibit the all-to-all interactions traditionally used to generate such entangled states. On the other hand, these systems exhibit exceedingly high degrees of experimental control over parameters such as temperature, spatial entropy, and itinerancy. In this work, we investigate spin squeezing in a highly coherent itinerant system of neutral atoms with magnetic dipole-dipole interactions. We achieve 7.1 dB of metrologically useful squeezing using finite-range spin-exchange interactions in an erbium quantum gas microscope, and we demonstrate that introducing atomic motion, realizing a dipolar 𝑡−𝐽 model, protects the spin sector coherence at low fillings, significantly improving the achievable spin squeezing in a 2D dipolar system. This work’s protocol can be implemented with most neutral atoms, opening the door to quantum-enhanced metrology in other itinerant dipolar systems, such as molecules or optical lattice clocks, and serves as a novel method for studying itinerant quantum magnetism with long-range interactions.
Isochronous Architecture-Based Voltage-Active Power Droop for Multi-Inverter Systems
This article proposes an isochronous architecture for parallel inverters with only voltage-active power droop (VP-D) control for improving active power sharing as well as plug-and-play of multi-inverter-based distributed energy resources (DERs). The isochronous framework obviates the need for an explicit regulation of the frequency while allowing for sharing of reactive power. The article shows that the detrimental effects of circulating currents between inverters can be addressed in the framework developed. The isochronous architecture is implemented by employing a GPS to disseminate clock timing signals that enable the microgrid to maintain the nominal system frequency. Small signal eigenvalue analysis of a Multi-inverter Microgrid system near the steady-state operating point is presented to evaluate the system stability. Moreover, unlike traditional droop-based methods, the isochronous strategy lends itself to analytical guarantees which are developed in the article. Furthermore, the effect of delays in receiving GPS clock signals by an inverter is experimentally characterized and an inverter isolation mechanism is proposed that disconnects inverters facing large GPS communication delays. Hardware experiments on an 1.2 kVA-prototype and controller-hardware-in-the-loop validation on the CIGRE distribution network are conducted to demonstrate the effectiveness of the proposed architecture towards active and reactive power sharing between inverters with load scenarios.
Transcriptome and Degradome Profiling Reveals a Role of miR530 in the Circadian Regulation of Gene Expression in Kalanchoë marnieriana
Crassulacean acid metabolism (CAM) is an important photosynthetic pathway for plant adaptation to dry environments. CAM plants feature a coordinated interaction between mesophyll and epidermis functions that involves refined regulations of gene expression. Plant microRNAs (miRNAs) are crucial post-transcription regulators of gene expression, however, their roles underlying the CAM pathway remain poorly investigated. Here, we present a study characterizing the expression of miRNAs in an obligate CAM species Kalanchoë marnieriana. Through sequencing of transcriptome and degradome in mesophyll and epidermal tissues under the drought treatments, we identified differentially expressed miRNAs that were potentially involved in the regulation of CAM. In total, we obtained 84 miRNA genes, and eight of them were determined to be Kalanchoë-specific miRNAs. It is widely accepted that CAM pathway is regulated by circadian clock. We showed that miR530 was substantially downregulated in epidermal peels under drought conditions; miR530 targeted two tandem zinc knuckle/PLU3 domain encoding genes (TZPs) that were potentially involved in light signaling and circadian clock pathways. Our work suggests that the miR530-TZPs module might play a role of regulating CAM-related gene expression in Kalanchoë.
Thermalization in the D1D5 CFT
It is generally agreed that black hole formation in gravity corresponds to thermalization in the dual CFT. It is sometimes argued that if the CFT evolution shows evidence of large redshift in gravity, then we have seen black hole formation in the CFT. We argue that this is not the case: a clock falling towards the horizon increases its redshift but remains intact as a clock; thus it is not `thermalized'. Instead, thermalization should correspond to a new phase after the phase of large redshift, where the infalling object turns into fuzzballs on reaching within planck distance of the horizon. We compute simple examples of the scattering vertex in the D1D5 CFT which, after many iterations, would lead to thermalization. An initial state made of two left-moving and two right-moving excitations corresponds, in gravity, to two gravitons heading towards each other. The thermalization vertex in the CFT breaks these excitations into multiple excitations on the left and right sides; we compute the amplitudes for several of these processes. We find secular terms that grow as $t^2$ instead of oscillating with $t$; we conjecture that this may be a feature of processes leading to thermalization.
Toward real-time optimization through model reduction and model discrepancy sensitivities
Optimization problems arise in a range of scenarios, from optimal control to model parameter estimation. In many applications, such as the development of digital twins, it is essential to solve these optimization problems within wall-clock-time limitations. However, this is often unattainable for complex systems, such as those modeled by nonlinear partial differential equations. One strategy for mitigating this issue is to construct a reduced-order model (ROM) that enables more rapid optimization. In particular, the use of nonintrusive ROMs—those that do not require access to the full-order model at evaluation time—is popular because they facilitate the computation of optimization solutions within the wall-clock time requirements. However, the optimization solution will be unreliable if the iterates move outside the ROM training data. This article proposes the use of hyper-differential sensitivity analysis with respect to model discrepancy (HDSA-MD) as a computationally efficient tool to augment ROM-constrained optimization and improve its reliability. The proposed approach consists of two phases: (i) an offline phase where several full-order model evaluations are computed to train the ROM, and (ii) an online phase where a ROM-constrained optimization problem is solved, a limited number of full-order model evaluations are computed, and HDSA-MD is used to enhance the optimization solution. Numerical results are demonstrated for two examples, atmospheric contaminant control and wildfire ignition location estimation, in which a ROM is trained offline using inaccurate atmospheric data. In conclusion, the HDSA-MD update yields a significant improvement in the ROM-constrained optimization solution using only one full-order model evaluation online with corrected atmospheric data.
A time-parallel method for scalable heat transfer simulations of additive manufacturing
Here, a major challenge in simulating the thermal behavior in additive manufacturing processes is the disparate length and time scales between transport phenomena occurring in the melt pool and the component. A common simulation approach relies on spatial decomposition for parallel computing, but due to the nature of heat transfer in AM, where most of the computational expenditure is localized near the melt pool, the computational speedup from spatial parallelization saturates quickly. Therefore, additional parallelism by means of time-domain decomposition is needed to fully take advantage of high-performance computing (HPC) resources. This work introduces a time-parallel method to improve the computational scalability of additive manufacturing simulations on HPC systems, while maintaining high temporal resolution of heat transfer near the melt pool. The method, inspired by the nonlinear paraexp formalism, performs an iterative superposition of nonlinear solutions to the initial value problem, integrating the heat equation across overlapping time-parallel intervals. For a single layer of the NIST AMB2018–01 L7 benchmark problem, the method achieves a 38.51x speedup in wall-clock time with a maximum error in the global temperature solution of 0.99%. This reduces the total solution time from 196.72 min to 5.11 min on 128 nodes of the ORNL Frontier supercomputer. The tradeoff between accuracy and total wall-clock time is investigated and recommendations for time-parallel deployment for AM problems are made.
In-pixel AI for lossy data compression at source for X-ray detectors
Integrating neural networks for data compression directly in the Read-Out Integrated Circuits (ROICs), i.e. the pixelated front-end, would result in a significant reduction in off-chip data transfer, overcoming the I/O bottleneck. Our ROIC test chip (AI-In-Pixel-65) is designed in a 65 nm Low Power CMOS process for the readout of pixelated X-ray detectors. Each pixel consists of an analog front-end for signal processing and a 10b analog-to-digital converter operating at 100KSPS. Here, we compare two non-reconfigurable techniques, Principal Component Analysis (PCA) and an AutoEncoder (AE) as lossy data compression engines implemented within the pixelated area. The PCA algorithm achieves 50$×$ compression, adds one clock cycle latency, and results in a 21% increase in the pixel area. The AE achieves 70$×$ compression, adds 30 clock cycle latency, and results in a similar area increase.