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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Sensitivity analysis of add-on price estimate for select silicon wafering technologies

The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

Mokashi, A. R.↗
NASA NTRS1982

System for slicing wafers

A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

Source record↗
NASA NTRS1985

Automatically Dressing Blades in Silicon-Wafer Cutting

Inserts incorporated in support beams for silicon ingots automatically "dress" cutting blade during wafer slicing. Segments of blade-dressing material placed at regular intervals in graphite beam. Blade cuts into segments and dressed without operator intervention and without interrupting regular machine operation. Manual dressing eliminated, and production rates increased.

Morrison, A. D.↗
NASA NTRS1986

Smoother Scribing of Silicon Wafers

Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

Danyluk, S.↗
NASA NTRS1986

Apparatus for edge etching of semiconductor wafers

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.↗
NASA NTRS1986

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Briglio, A.↗
NASA NTRS1986

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Bauhahn, P.↗
NASA NTRS1988

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.↗
NASA NTRS1988

Temperature control in wafer-level testing of large multi-segment electromigration test structures

The paper describes two methods for maintaining a constant metallization temperature throughout a wafer-level isothermal electromigration test of large multisegment test structures where Joule-heating is high and chip to chuck thermal contact is poor. In the first method, an initial calibration of Joule heating versus metal temperature is carried out. During the isothermal electromigration test, the Joule heating is continuously monitored and the chuck temperature is adjusted based on the calibration results to maintain a constant metal temperature. In the second method, temperature sensors are fabricated on the chip and then the sensors are used to monitor the chip temperature directly. The chuck temperature is then adjusted as needed.

Zamani, Nasser↗
NASA NTRS1992

Visible luminescence from silicon wafers subjected to stain etches

Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

Fathauer, R. W.↗
NASA NTRS1992

Sputter deposition of SiC coating on silicon wafers

A study is conducted of the effect of substrate temperature during coating on the properties of coated SiC films on Si wafers, using a scratch test technique. While specimen temperature during coating has little effect on deposition rate, it significantly affects the durability of the coating. Scratch test damage to both film coating and substrate decreased with increasing deposition temperature, perhaps due to the rapid diffusion of the deposited atoms.

Robson, M. T.↗
NASA NTRS1992

Piezoresistive stress sensors on (110) silicon wafers

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

Kang, Y. L.↗
NASA NTRS1996

Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Wronosky, John B.↗
NASA NTRS2005

Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F

Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

Dunlap, Patrick H.↗
NASA NTRS1995

Ultra-Low Noise HEMT Device Models: Application of On-Wafer Cryogenic Noise Analysis and Improved Parameter Extraction Techniques

Significant advances in the development of HEMT technology have resulted in high performance cryogenic low noise amplifiers whose noise temperatures are within an order of magnitude of the quantum noise limit. Key to the identification of optimum HEMT structures at cryogenic temperatures is the development of on-wafer noise and device parameter extraction techniques. Techniques and results are described.

electronic materials↗
NASA NTRS1988

Multi-wafer slicing with a fixed abrasive

A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

Schmid, Frederick↗
NASA NTRS2014

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Hoenk, Michael E.↗