SEARCH · Engineering Papers

Results for “VLSI circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 145 records · Page 8

All sources NASA NTRS DOE OSTI

NASA NTRS1994

Electrostatically suspended and sensed micro-mechanical rate gyroscope

The goal of this work is development of fully electrostatically suspended and rebalancing angular rate sensing micro-gyroscope fabricated according to standard VLSI techniques. Fabrication of test structures is proceeding. Off chip electronics for the electrostatic sensing and driving circuits has been tested. The prototype device will be assembled in a hybrid construction including the FET input stages of the sensors.

Torti, R.↗

NASA NTRS1982

High density circuit technology, part 1

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

Wade, T. E.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, H. T.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

Lin, Shu↗

NASA NTRS1983

A parallel VLSI architecture for a digital filter using a number theoretic transform

The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

Truong, T. K.↗

NASA NTRS1983

Automatic hardware synthesis

The complexity of the circuit that can fit on an integrated circuit (IC) chip has reached the level of a million transistors with the advent of Very-Large-Scale Integration (VLSI). Several automatic synthesis systems have evolved that 'aid' the human designer in managing this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a high-level design specification into a lower level design specification that includes more structural details, leading to the physical design of the IC. The characteristics of ten automatic synthesis systems are summarized.

Shiva, S. G.↗

NASA NTRS1987

Implementation of optical interconnections for VLSI

This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

Wu, Wennie H.↗

NASA NTRS1988

Implementing neural nets with programmable logic

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Vidal, Jacques J.↗

NASA NTRS1988

VLSI Architecture Of A Binary Up/Down Counter

Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.

Hsu, In-Shek↗

NASA NTRS1991

Controlling state explosion during automatic verification of delay-insensitive and delay-constrained VLSI systems using the POM verifier

Delay-insensitive VLSI systems have a certain appeal on the ground due to difficulties with clocks; they are even more attractive in space. We answer the question, is it possible to control state explosion arising from various sources during automatic verification (model checking) of delay-insensitive systems? State explosion due to concurrency is handled by introducing a partial-order representation for systems, and defining system correctness as a simple relation between two partial orders on the same set of system events (a graph problem). State explosion due to nondeterminism (chiefly arbitration) is handled when the system to be verified has a clean, finite recurrence structure. Backwards branching is a further optimization. The heart of this approach is the ability, during model checking, to discover a compact finite presentation of the verified system without prior composition of system components. The fully-implemented POM verification system has polynomial space and time performance on traditional asynchronous-circuit benchmarks that are exponential in space and time for other verification systems. We also sketch the generalization of this approach to handle delay-constrained VLSI systems.

Probst, D.↗

NASA NTRS1981

Impact of VLSI/VHSIC on satellite on-board signal processing

Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

Aanstoos, J. V.↗

NASA NTRS2010

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.1 and at least one other matrix, with first equation including X.sup.1Y, X.sup.1A, and X.sup.1P, and the second equation including X.sup.1A and X.sup.1P.

Jain, Jitesh↗

NASA NTRS2012

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.-1 and at least one other matrix, with first equation including X.sup.-1Y, X.sup.-1A, and X.sup.-1P, and the second equation including X.sup.-1A and X.sup.-1P.

Jain, Jitesh↗

NASA NTRS1990

Neural net diagnostics for VLSI test

This paper discusses the application of neural network pattern analysis algorithms to the IC fault diagnosis problem. A fault diagnostic is a decision rule combining what is known about an ideal circuit test response with information about how it is distorted by fabrication variations and measurement noise. The rule is used to detect fault existence in fabricated circuits using real test equipment. Traditional statistical techniques may be used to achieve this goal, but they can employ unrealistic a priori assumptions about measurement data. Our approach to this problem employs an adaptive pattern analysis technique based on feedforward neural networks. During training, a feedforward network automatically captures unknown sample distributions. This is important because distributions arising from the nonlinear effects of process variation can be more complex than is typically assumed. A feedforward network is also able to extract measurement features which contribute significantly to making a correct decision. Traditional feature extraction techniques employ matrix manipulations which can be particularly costly for large measurement vectors. In this paper we discuss a software system which we are developing that uses this approach. We also provide a simple example illustrating the use of the technique for fault detection in an operational amplifier.

Lin, T.↗

DOE OSTI2024

Post-processing of phase change material in a zero-change commercial silicon photonic process

Integration of phase change material (PCM) with photonic integrated circuits can transform large-scale photonic systems by providing non-volatile control over phase and amplitude. The next generation of commercial silicon photonic processes can benefit from the addition of PCM to enable ultra-low power, highly reconfigurable, and compact photonic integrated circuits for large-scale applications. Despite all the advantages of PCM-based photonics, today’s commercial foundries do not provide them in their silicon photonic processes yet. We demonstrate the first-ever electrically programmable PCM device that is monolithically post-processed in a commercial foundry silicon photonics process using a few fabrication steps and coarse-resolution photolithography. These devices achieved 1.4 dB/μm of amplitude switching contrast using a thin layer of 12.5 nm GeSbTe in this work. We have also characterized the reconfiguration speed as well as repeatability of these devices over 20,000 switching cycles. Our solution enables non-volatile photonic VLSI systems that can be fabricated at low cost and high reliability in a commercial foundry process, paving the way for the development of non-volatile programmable photonic integrated circuits for a variety of emerging applications.

Optics↗

DOE OSTI2024

AstroPix4 — a novel HV-CMOS sensor developed for space based experiments

For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm 2 can currently not be reached due to the digital consumption of 3.08 mW/cm 2 , while the analog power consumption of 1.04 mW/cm 2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm 2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).

47 OTHER INSTRUMENTATION↗

NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗

DOE OSTI2021

Quantum Divide and Compute: Exploring the Effect of Different Noise Sources

Abstract Our recent work (Ayral et al. in Proceedings of IEEE computer society annual symposium on VLSI, ISVLSI, pp 138–140, 2020. 10.1109/ISVLSI49217.2020.00034 ) showed the first implementation of the Quantum Divide and Compute (QDC) method, which allows to break quantum circuits into smaller fragments with fewer qubits and shallower depth. This accommodates the limited number of qubits and short coherence times of quantum processors. This article investigates the impact of different noise sources—readout error, gate error and decoherence—on the success probability of the QDC procedure. We perform detailed noise modeling on the Atos Quantum Learning Machine, allowing us to understand tradeoffs and formulate recommendations about which hardware noise sources should be preferentially optimized. We also describe in detail the noise models we used to reproduce experimental runs on IBM’s Johannesburg processor. This article also includes a detailed derivation of the equations used in the QDC procedure to compute the output distribution of the original quantum circuit from the output distribution of its fragments. Finally, we analyze the computational complexity of the QDC method for the circuit under study via tensor-network considerations, and elaborate on the relation the QDC method with tensor-network simulation methods.

97 MATHEMATICS AND COMPUTING↗