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Design, Analysis, Comparison, and Experimental Validation of Insulated Metal Substrates for High-Power Wide-Bandgap Power Modules
Direct bonded copper (DBC) substrates used in power modules have limited heat spreading and manufacturing capability due to ceramic properties and manufacturing technology. The ceramic and copper bonding is also subject to high mechanical stress due to coefficient of thermal expansion mismatch between the copper and the ceramic. For wide-bandgap (WBG) devices, it is of interest exploring new substrate technologies that can overcome some of the challenges of direct bonded copper substrates. In this technical paper, the design, analysis, and comparison of insulated metal substrates (IMSs) for high-power wide-bandgap semiconductor-based power modules are discussed. This paper starts with technical description and discussion of state-of-the-art DBC substrates with different ceramic insulators such as aluminum nitride (AlN), Al 2 O 3 , and Si 3 N 4 . Next, an introduction of IMSs and their material properties, and a design approach for SiC (silicon carbide) metal-oxide-semiconductor field-effect transistor (MOSFET)-based power modules for high-power applications is provided. The influence of dielectric thickness on the power handling capability of the substrate are also discussed. The designed IMS and DBC substrates were characterized in terms of steady-state and transient thermal performance using finite element simulation. Finally, the performance of the IMS and DBC are validated in an experimental setup under different loading and cooling temperature conditions. We report the simulation and experimental results showed that the IMS can provide high steady-state thermal performance for high-power modules based on SiC MOSFETs. Furthermore, the IMS provided enhanced transient thermal performance, which provided a reduced junction temperature when the module is operated at low fundamental output frequencies in traction drive systems.
1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop
Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. Here, the BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.
7.2 kV Three-Port SiC Single-Stage Current-Source Solid-State Transformer With 90 kV Lightning Protection
This article proposes a multiport modular single-stage current-source solid-state transformer (SST) for applications like photovoltaic, energy storage integration, electric vehicle fast charging, data center, etc. The 7.2 kV 50 kVA current-source SST consists of five input-series output-parallel modules, each based on 3.3 kV SiC reverse-blocking MOSFET-plus-diode modules. The proposed SST has some unique features. First, compared to the voltage-source or matrix converter-based SSTs, the current-source SST has a unique advantage of single-stage isolated AC/DC or AC/AC conversion with an inductive DC link, but no medium-voltage (MV) AC experiments have been reported. This article for the first time demonstrates MV AC current-source SST up to 7.5 kV peak. Second, the multiport SST has a buffer port for active power decoupling (APD) or energy storage integration. The double-line-frequency power ripple from single-phase AC grid normally results in a large capacitor size in MV SSTs. The APD scheme is proposed in MV applications for the first time to enable a reduced DC link and the electrolytic capacitor-less SST with high reliability. Third, as a direct grid-connected converter without line-frequency transformer, insulation and protection are critical. A medium-frequency transformer design passes 55 kV basic-insulation level (BIL) and 60 kV high potential dielectrics withstand test with only 0.09% leakage inductance. Importantly, a lightning protection scheme is presented to protect the SST itself from 90 kV BIL impulse. Fourth, the proposed current-source SST topology is a modular soft-switching solid-state transformer (M-S4T) with full-range zero-voltage switching and controlled dv/dt for low electromagnetic interference. Furthermore, these concepts are verified in a three-port M-S4T prototype with forced oil cooling under single-module, stacked-module, steady-state, and dynamic operations.
SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)
This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.
Instability Issue of Paralleled Dies in an SiC Power Module in Solid-State Circuit Breaker Applications
Paralleled dies in a power module could have instability issues during high current switching transients. Here, the instability is caused by the differential-mode oscillation among paralleled MOSFETs. Conventional analyses of paralleled MOSFETs’ stability are normally limited to a single operating point, which ignores the influences of the switching trajectory and nonlinear device parameters on stability. This article reveals that the switching trajectory can significantly influence parallel stability. The analysis is improved by solving eigenvalues of state-space modeling system matrices of all operating points that the switching trajectory goes through considering nonlinear device parameters. Higher voltage and current stresses result in greater real parts of complex eigenvalues, which explains why the paralleled MOSFETs are more unstable with higher voltage and current stresses. To improve stability in solid-state circuit breaker applications, we propose a method to manipulate the switching trajectory to avoid the unstable region where the conventional hard switching trajectory normally goes through. Experimental results show that the turn- off current capability can be increased from ~five times of rated current with the gate oscillation using the conventional turn- off trajectory to ~ten times of rated current without the gate oscillation using the optimal turn- off trajectory.
A Smart Silicon Carbide Power Module With Pulse Width Modulation Over Wi-Fi and Wireless Power Transfer-Enabled Gate Driver, Featuring Onboard State of Health Estimator and High-Voltage Scaling Capabilities
A wide range of utility applications require controllable switches with features such as high-voltage blocking and high-current carrying capacity, especially at high pulse width modulation (PWM) frequency. Low- and medium-voltage utility applications such as motor drives and flexible AC transmission systems as well as solid state transformers could also benefit from a low-cost high-voltage switching module. Wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) metal oxide semiconductor field effect transistors (MOSFETs) are considered to be the present and next-generation device choices, although they have limitations. For relatively high-voltage applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low-voltage regime. This manuscript proposes a new half-bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in high-voltage applications. Constructed from bare SiC dies, this half-bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold, and cooling, (3) integrated gate driver module with pulse width modulation (PWM) over wi-fi to eliminate the need for low-voltage signals, (4) wireless power transfer (WPT)-enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state-of-health (SOH) estimator module. The entire architecture has been designed and built at the National Renewable Energy Laboratory (NREL) in Golden, CO.
Rapid Prototyping Techniques for Organic Direct-Bonded-Copper Power Modules
Organic Direct-Bonded-Copper (ODBC) is a novel packaging technology for power modules which allows higher flexibility in layout design. In this work, a set of rapid prototyping techniques are developed for ODBC modules based on a polyimide dielectric material. These techniques enable fast and low-cost fabrication of modules with 3-Dimensional (3D) layout features. An example half-bridge (HB) silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) module is designed and prototyped using the proposed techniques aiming at ultra-low power loop inductance. Finite element analysis (FEA)-circuit co-simulations results and experimental results validate an approximately 0.71nH power loop inductance for the example module design.
Drivers for paralleled semiconductor switches
An apparatus includes a plurality of parallel-connected semiconductor switches (e.g., silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) or other wide-bandgap semiconductor switches) and a plurality of driver circuits having outputs configured to be coupled to control terminals of respective ones of the plurality of semiconductor switches and configured to drive the parallel-connected semiconductor switches responsive to a common switch state control signal. The driver circuits may have respective different power supplies, which may be adjustable. Respective output resistors may couple respective ones of the driver circuits to respective ones of the semiconductor switches. The output resistors may be adjustable.
SiC JFET Transistor Circuit Model for Extreme Temperature Range
A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.
Low Cost High-Performance HRE-Free 3-in-1 Electric Drive Unit
The project team completed work to expand upon American Axle & Manufacturing’s (AAM) baseline technology and develop a high-speed, AC induction electric drive unit (EDU) with total direct-oil-cooling and integrated power electronics. The project accelerated advancements in EDU technology by allowing AAM to build upon the progress made in developing the underlying baseline technologies. The following seven improvements to AAM’s baseline technology were implemented in this research and development program: 1) Increased speed (30k RPM) AC induction motor, 2) Silver-sintering of discrete silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFET) to heat sinks, 3) Electrically insulated rotor bars, 4) Optimized lamination steel, 5) EDU-integrated 650VDC inverter package, 6) Over-molded stator with molded liners, and 7) 650VDC power-dense stator design. The successful development of the technology resulted in a meaningful cost reduction for EDU systems in the market. Coupled with falling battery system costs, lower EDU costs will likely accelerate the market acceptance and related production scaling of battery electric vehicles. The objective of this project was to research, develop, and test a Heavy Rare Earth (HRE)-free 3-In-1 electric drive unit (EDU) that has class leading power density and cost. The key technologies to be developed were anticipated to meet or exceed the Department of Energy (DOE) targets of a cost ≤ $\$$7/kilowatt (kW), power density ≥ 12 kW/liter, and operating voltage ≥ 600 VDC.
Power Module Precursors and Prognostics
This project focuses on finding and utilizing electrical properties (precursors) of power electronic devices and modules whose changes have strong correlations with different modes and levels of degradations in order to realize online and lightweight state of health evaluation and fault diagnosis. Results from this project will contribute to higher safety, reliability, and power density of power electronic components. The approaches mainly include reviewing academic literature and industry practices for state of the art precursor identification and extraction, accelerated life cycles (ALC) of various power modules to create different degradations in-house, and developing techniques for gate-driver-integratable precursor detection circuit. In FY24, the results includes two sets of definitively detected aging precursors (on-state resistance and gate threshold voltage) for two sets of power modules respectively, controlled accelerated lifetime cycling of multiple silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) modules, and the development and validation of a gate voltage detection system.
Thermal Optimization and Experimental Demonstration of a Silicon Carbide, Half-Bridge Power Module
This paper describes modeling and experimental work to design and demonstrate a silicon carbide (SiC), single-side-cooled power module. Two SiC metal-oxide-semiconductor field-effect transistors (MOSFET) were used for each switch position and packaged on a metalized ceramic substrate. Thermal modeling was first conducted to optimize the module packaging to minimize junction-to-fluid thermal resistance and device temperature variations. This procedure identified the optimal device placement and baseplate thickness to maximize thermal performance. A heat exchanger - incorporating impinging jets of water-ethylene glycol - was designed to cool the module's baseplate to minimize thermal resistance and pumping power. The heat exchanger used relatively low fluid velocities (<1.5 m/s) to minimize erosion-corrosion effects and relatively large fluid channel sizes (>=1 mm) to prevent clogging. The power module concept was fabricated, and experiments were conducted to measure its thermal performance. Direct current was used to power the module devices, and junction temperatures were measured via device temperature-sensitive parameters. The experimental results were found to be in good agreement with model predictions (within 2%) and yielded junction-to-fluid thermal resistance values as low as about 15 mm2 K/W at relatively low pumping power values. The results demonstrate the improved performance associated with jet impingement cooling and represent an improvement over existing channel-flow-type cold plates, which can enable improvements to power density and reliability.
Solid state protective smart plug device
A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.
Space Radiation Effects on SiC Power Device Reliability
Heavy-ion radiation can result in silicon carbide power device degradation and/or catastrophic failure. Test procedures and data interpretation must consider the impact that heavy-ion induced off-state leakage current increases will have on subsequent single-event effect susceptibility and testability. On orbit, reliable performance in the presence of increased off-state leakage currents due to cumulative ion-induced non-catastrophic single-event effects must be assured over the mission lifetime. This work presents a large body of heavy-ion test data for different diode, power MOSFET, and JFET devices. Susceptibility to single-event effects is compared between SiC and Si power devices. Initial recommendations on heavy-ion radiation test methods for silicon carbide power devices are made and radiation hardness assurance is discussed with the goal of moving one step closer to reliably getting this technology off the ground into a broad array of spacecraft and instruments that will benefit from its unique capabilities.
Packaging Development for a 1200V SiC BiDFET Switch Using Highly Thermally Conductive Organic Epoxy Laminate
A novel 1.2 kV/10A, 4H-SiC monolithic, bidirectional switch has been developed for use in cycloconverter applications to facilitate high-frequency direct AC-to-AC power conversion and enables new power converter topologies. A new packaging solution, utilizing a 100 µm flexible polyimide organic laminate substrate is developed to mitigate thermo-mechanical stress during power cycling and enable smaller form factor and lower cost. Multiphysics simulations and static tests were conducted to show performance characterization of the module and compare it against metallic substrates. A new organic laminate epoxy resin composite dielectric (ERCD) is also evaluated for superior thermal performance and shows 63% reduction in junction to case resistance compared to DBC substrates.
Silicon Carbide Power Devices and Integrated Circuits
An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.
Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs
All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.