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The digital filtering algorithm of W. D. Little, which employs a large RAM to obtain high speed, is implemented in a simple hardware configuration. The nonrecursive version of this filter is compared to the counting digital filter and found to be competitive for low-order filters up to order 7 (8 coefficients).
A concept for containing the shock inputs due to hydrodynamic ram caused by an impacting projectile within a fuel cell is discussed. This is to provide a buffering layer of foam, flexible, rigid or a combination thereof, which is sealed from the liquid. A program is described in which this buffering concept was tested. The effectiveness of a novel muzzle-mounted, 'tumble', test device is shown.
Several types of CMOS static random access memories (RAMs) have been tested in a cyclotron for susceptibility to single event upsets and latchup such as might occur in earth orbit or interplanetary space. No upsets have been observed for neutron fluences of 10 to the 11th n/sq cm and higher or proton fluences of 10 to the 9th protons/sq cm.
A model has been developed which predicts the relative susceptibility of bipolar RAMs to heavy ion and proton upset. During the course of evaluating this model, physical and electrical variations were also evaluated indicating that the minimum internal signal level is the primary upset susceptibility indicator. Unfortunately, all of the physical and electrical variations expected during a normal product development cycle are in direct opposition to improved high-energy particle upset tolerance. Hence, a trade-off between highly susceptible, low power (medium speed) devices must be made against the less susceptible, higher power (high speed) equivalent device, taking into account the systems trade-off with respect to system power, software, error correction procedures and/or circuit redundancy.
A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.
Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.
Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.
The first measurement of single event upset (SEU) for complementary GaAs static RAMs caused by heavy ions is reported. Upset cross-sections of the circuits for 28 MeV oxygen ions are reported as well as the linear energy transfer (LET) threshold established by using 170 MeV oxygen ions at various angles of beam incidence.
Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.
Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.
Reverse-flow HEXFET(R) minimizes voltage drop and power dissipation. HEXFET(R) scheme reduces voltage drop by approximately 80 percent. Design for power tap for random-access memory (RAM) has potential application in digital systems.
A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
NASA's Space Station Maintenance Planning and Analysis (MP&A) Study is a step in the overall Space Station Program to define optimum approaches for on-orbit maintenance planning and logistics support. The approach used in the MP&A study and the analysis process used are presented. Emphasis is on maintenance activities and processes that can be accomplished on orbit within the known design and support constraints of the Space Station. From these analyses, recommendations for maintainability/maintenance requirements are established. The ultimate goal of the study is to reduce on-orbit maintenance requirements to a practical and safe minimum, thereby conserving crew time for productive endeavors. The reliability, availability, and maintainability (RAM) and operations performance evaluation models used were assembled and developed as part of the MP&A study and are described. A representative space station system design is presented to illustrate the analysis process.
Proposed random-access-memory (RAM) addressing system, in which memory linked optically to read/write logic circuits, greatly increases computer operating speed. System - comprises addressing circuits including numerous lasers as signal sources, numerous optical gates including optical detectors associated with memory cells, and holographic element to direct light signals to desired memory-cell locations - applied to high-capacity digital systems, supercomputers, and complex microcircuits.
Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.
NGC 4438 is the highly HI deficient peculiar spiral in the center of the Virgo cluster. Observations are given of the neutral hydrogen emission obtained with the Very Large Array (VLA) in the D-array configuration. These observations map out the total HI as determined from single dish measurements, and show the hydrogen to be confined to a region about one third the size of the optical disk and displaced to the side of the galaxy opposite M87. The hydrogen content of the galaxy is over an order of magnitude less than that expected for a galaxy of its type. The data suggest that the HI deficiency is a result of ram pressure stripping of the gas in the outer regions of the galaxy by the hot intracluster medium after being tidally perturbed.
A computational study of the ram accelerator, a ramjet-in-tube device for accelerating projectiles to ultrahigh velocities, is presented. The analysis is performed using a fully implicit TVD scheme that efficiently solves the Reynolds-averaged Navier-Stokes equations and the species continuity equations associated with a finite rate combustion model. The present results indicate that viscous effects are of primary importance in all the cases studied, shock-induced combustion always started in the boundary layer. The effects of Mach number, mixture composition, pressure and tubulence are investigated for various configurations. Two types of combustion processes, one stable and the other unstable, were observed depending on the inflow conditions. The possibility of stabilizing the detonation wave by means of a backward facing step is also investigated. Two numerical techniques were tested: vector extrapolation, to accelerate convergence, and a diagonal formulation that eliminates the expense of inverting large block matrices which arise in chemically reacting flows.
A novel RAM architecture supporting concurrent memory access and on-chip testing (CMAT) is proposed. A large-capacity memory chip is decomposed into test neighborhoods (TNDs), each of which is tested independently. When there are data stored in a TND, the data are saved into a buffer before testing the TND, and the TND's contents are restored using buffered data after testing the TND. If an external request is not made to the TND, the request can be directed to the addressed memory cells. Otherwise, the buffered data can be loaded back into the TND, or the request is detoured to a corresponding buffer. By deriving an analytical model, the performance penalty and hardware overhead of the CMAT architecture are shown to be very small.