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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,405 records · Page 78
All sourcesNASA NTRSDOE OSTI
DOE OSTI2016

High-speed X-ray imaging pixel array detector for synchrotron bunch isolation

A wide-dynamic-range imaging X-ray detector designed for recording successive frames at rates up to 10 MHz is described. X-ray imaging with frame rates of up to 6.5 MHz have been experimentally verified. The pixel design allows for up to 8–12 frames to be stored internally at high speed before readout, which occurs at a 1 kHz frame rate. An additional mode of operation allows the integration capacitors to be re-addressed repeatedly before readout which can enhance the signal-to-noise ratio of cyclical processes. This detector, along with modern storage ring sources which provide short (10–100 ps) and intense X-ray pulses at megahertz rates, opens new avenues for the study of rapid structural changes in materials. The detector consists of hybridized modules, each of which is comprised of a 500 µm-thick silicon X-ray sensor solder bump-bonded, pixel by pixel, to an application-specific integrated circuit. The format of each module is 128 × 128 pixels with a pixel pitch of 150 µm. In the prototype detector described here, the three-side buttable modules are tiled in a 3 × 2 array with a full format of 256 × 384 pixels. Lastly, we detail the characteristics, operation, testing and application of the detector.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Fast digital lossy compression for X-ray ptychographic data

Increases in X-ray brightness from synchrotron light sources lead to a requirement for higher frame rates from hybrid pixel array detectors (HPADs), while also favoring charge integration over photon counting. However, transfer of the full uncompressed data will begin to constrain detector design, as well as limit the achievable continuous frame rate. Here a data compression scheme that is easy to implement in a HPAD's application-specific integrated circuit (ASIC) is described, and how different degrees of compression affect image quality in ptychography, a commonly employed coherent imaging method, is examined. Using adaptive encoding quantization, it is shown in simulations that one can digitize signals up to 16383 photons per pixel (corresponding to 14 bits of information) using only 8 or 9 bits for data transfer, with negligible effect on the reconstructed image.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2021

High-energy micrometre-scale pixel direct conversion X-ray detector

The objective of this work was to fabricate and characterize a new X-ray imaging detector with micrometre-scale pixel dimensions (7.8 µm) and high detection efficiency for hard X-ray energies above 20 keV. A key technology component consists of a monolithic hybrid detector built by direct deposition of an amorphous selenium film on a custom designed CMOS readout integrated circuit. Characterization was carried out at the synchrotron beamline 1-BM-B at the Advanced Photon Source of Argonne National Laboratory. The direct conversion detector demonstrated micrometre-scale spatial resolution with a 63 keV modulation transfer function of 10% at Nyquist frequency. In addition, spatial resolving power down to 8 µm was determined by imaging a transmission bar target at 21 keV. X-ray signal linearity, responsivity and lag were also characterized in the same energy range. Finally, phase contrast edge enhancement was observed in a phase object placed in the beam path. This amorphous selenium/CMOS detector technology can address gaps in commercially available X-ray detectors which limit their usefulness for existing synchrotron applications at energies greater than 50 keV; for example, phase contrast tomography and high-resolution imaging of nanoscale lattice distortions in bulk crystalline materials using Bragg coherent diffraction imaging. Here, the technology will also facilitate the creation of novel synchrotron imaging applications for X-ray energies at or above 20 keV.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Nano-laminography with a transmission X-ray microscope

Nano-laminography combines the penetrating power of hard X-rays with a tilted rotational geometry to deliver high-resolution, three-dimensional images of laterally extended, flat specimens that are otherwise incompatible with, or difficult to image using, conventional nano-tomography. In this work, we demonstrate a full-field, X-ray nano-laminography system implemented with the transmission X-ray microscope at beamline 32-ID of the upgraded Advanced Photon Source at Argonne National Laboratory, USA. By rotating the sample around an axis inclined by 20° to the incident beam, the technique minimizes the long optical path lengths that would otherwise generate excessive artifacts when planar samples are imaged edge-on. The efficiency of the technique is demonstrated with 50 nm spatial resolution and minute-scale temporal resolution 3D imaging of a planar integrated circuit sample and targeted imaging of an individual particle within a powder sample, where mounting procedures are typically challenging in regular nano-tomography. The sample mounting strategy, data acquisition, and reconstruction method will also be discussed.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2026

Gaia: segmented germanium detector for high-energy X-ray fluorescence and spectroscopic imaging

We present Gaia, a monolithic array of 96 high-purity germanium pixel detectors integrated with a custom low-noise application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA)-based data acquisition system. The sensor operates at ∼100 K using a commercial closed-cycle cryocooler, with the in-vacuum electronics thermally isolated from the cold finger to ensure thermal stability. The system demonstrates an average energy resolution of 711 eV at 122 keV, measured using a 57 Co source, and 253 eV at 5.89 keV, measured with 55 Fe across all channels. The readout architecture incorporates a high-performance FPGA paired with a dual-core ARM processor, forming a complete embedded Linux-based computing platform. Communication between the processor and FPGA is handled via memory-mapped I/O, and data are streamed over high-speed gigabit Ethernet. A full-scale 384-pixel Gaia detector, based on this 96-element module, is currently under fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Single Event Effects Test Facility Options at the Oak Ridge National Laboratory

Increasing use of microelectronics of ever diminishing feature size in avionics systems has led to a growing Single Event Effects (SEE) susceptibility arising from the highly ionizing interactions of cosmic rays and solar particles. Single event effects caused by atmospheric radiation have been recognized in recent years as a design issue for avionics equipment and systems. To ensure a system meets all its safety and reliability requirements, SEE induced upsets and potential system failures need to be considered, including testing of the components and systems in a neutron beam. Testing of integrated circuits (ICs) and systems for use in radiation environments requires the utilization of highly advanced laboratory facilities that can run evaluations on microcircuits for the effects of radiation. This paper provides a background of the atmospheric radiation phenomenon and the resulting single event effects, including single event upset (SEU) and latch up conditions. A study investigating requirements for future single event effect irradiation test facilities and developing options at the Spallation Neutron Source (SNS) is summarized. The relatively new SNS—with its 1.0 GeV proton beam, typical operation of 5000 h per year, expertise in spallation neutron sources, user program infrastructure, and decades of useful life ahead—is well suited for hosting a world-class SEE test facility in North America. Emphasis was put on testing of large avionics systems while still providing tunable high flux irradiation conditions for component tests. Makers of ground-based systems would also be served well by these facilities. Three options are described; the most capable, flexible, and highest-test-capacity option is a new stand-alone target station using about one kW of proton beam power on a gas-cooled tungsten target, with dual test enclosures. Less expensive options are also described.

Digital avionics↗
DOE OSTI2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit data streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across application kernels. However, emerging streaming applications at the edge (scientific instruments, sensor networks, network processing) perform much more than digital signal processing and often are data and input dependent. This leads to extremely variable kernel execution times, severely impacting the throughput of the entire pipeline if resources are only statically allocated. Therefore, in this paper, we propose DRIPS — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We present a unified compiler framework to facilitate the mapping of a given streaming application onto the DRIPS CGRA architecture. The experimental results show that DRIPS achieves an average throughput improvement of 1.46$\times$ across a set of representative applications over a statically partitioned solution. The additional area overhead to enable dynamic rebalancing consumes 16.34% of the entire area for a 5x5 CGRA prototype.

Tan, Cheng↗
DOE OSTI2018

Two-Layer Predictive Controller for V2G and G2V Services Using on Wireless Power Transfer Technology

This paper presents a comprehensive solution that allows electric vehicles (EV) to autonomously charge and discharge their batteries wirelessly during long term parking and/or the transient stops. A two-layer power-flow controller for bidirectional wireless power transfer system (BWPTS) in EVs applications is proposed. The proposed controller can manage the bidirectional power-flow between EV and surrounding infrastructures such as power grid, home microgrid, building micro-grid, road or another vehicle. It consists of two levels of control; the first is responsible for communicating with the surrounding infrastructures and gathering information from driver, charging station, power grid and battery management system and then, based on these information, it estimates the EV's psychological price as a function of its battery's state-of-charge (SOC) and compares it with the energy price to decide whether to charge, discharge or abstain, and how much the charging or discharging rate. The second layer receives the reference signal from the first one and generates the control parameters for two synchronized resonant converters (one is on the vehicle side and the other is on the grid side) to provide the requited power-flow. The proposed controller is adaptively estimating the system parameters to consider the misalignment conditions effects on the system performance. The parameter estimation is achieved using only one voltage sensor. The second layer control is designed based on a new analytical modeling for the power flow in the system. For verification purposes, a prototype for BWPTS was built and driven by the proposed controller, which was implemented using a field-programmable gate array (FPGA) integrated circuit. The proposed controller provides very fast and stable response during both the transient and steady state operation in comparison with the conventional PI controller.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across kernels. However, streaming applications often are data-dependent, leading to variable kernel execution times depending on the input data and impacting the throughput of the entire pipeline if resources are statically allocated. Therefore, in this paper, we discuss the design of DynPaC — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We discuss the required software and hardware components to manage partial dynamic reconfiguration. We demonstrate that by supporting partial dynamic reconfiguration, we can obtain an average speedup of 1.44X for a representative set of applications w.r.t. static partitioning, with a limited area overhead (6.4% of the entire chip).

Tan, Cheng↗
DOE OSTI2023

Foundry-fabricated silicon source of broadband polarization entanglement

We present a CMOS-fabricated photonic integrated circuit tailored to the generation of ultrabroadband polarization-entangled photons. This fully on-chip source leverages a novel design combining polarization splitter-rotators and a bidirectionally pumped microring resonator to produce high-fidelity polarization Bell states over 115 frequency-bin pairs spaced 38.4 GHz apart.

Miloshevsky, Alex↗
DOE OSTI2022

Design and Challenges of Edge Computing ASICs on Front-End Electronics

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks (ANNs) in the front-end electronics, and the design of custom integrated circuits (ASICs), comes with challenges. In addition, detectors have to operate with limited power budget and implement complex functionalities in a very dense space. They often are exposed to extreme conditions as they work in high-radiation environments and/or cryogenic temperatures. This paper presents examples of applications and design methodologies for in-situ ANNs, along with the challenges of retaining the fidelity of the trained networks. For illustration, we use the problem of estimating the energy deposited by the radiation from digitized waveforms. The proposed implementation starts with an ML algorithm trained in Qkeras and eventually leads to an equivalent ASIC implementation. The associated design challenges in realizing energy and area efficient implementations in CMOS processes are reviewed. Novel approaches that employ hybrid technologies (combination of CMOS with memristors), in-memory computing models, and bio-inspired spiking neural networks are also highlighted

47 OTHER INSTRUMENTATION↗
DOE OSTI2013

Non-Destructive State Machine Reverse Engineering

Most of the integrated circuits (ICs) that are in electronic systems today are based on state machines. We are taking advantage of this to develop a hardware reverse engineering method that discovers the IC’s underlying state machine, rather than its transistors and gates. While there are other methods for destructively reverse engineering ICs or for non-destructively characterizing ICs, our method offers a fast and accurate analysis while remaining non-destructive. To do this, we present an intelligent brute-force method of exploring the logic of the IC using only the input and outputs designed into the IC - the I/O pins. From this exploration, we can apply a folding algorithm to discover the designed state machine.

counterfeit↗
DOE OSTI2015

Inorganic Materials and Assembly Techniques for Flexible and Stretchable Electronics

In recent years, important progress has been made in developing design strategies, materials, and associated assembly techniques that provide empowering approaches to electronics with unconventional formats, ones that allow useful but previously hard to realize attributes of function. Notable examples of the progress made include: light weight, large area, high performance electronics, optics, and photonics; electronic and optical systems with curvilinear shapes and capacities for accommodating demanding forms of mechanical flexure; new device form factors for use in sensing and imaging; the integration of high performance electronics in 3-D with demanding nanometer design rules; functional bioresponsive electronics; and advanced hybrid materials systems for lighting, energy storage, and photovoltaic energy conversion. In this report we highlight advances that are enabling such promising capabilities in technology-specifically, the fabrication of device elements using high performance inorganic electronic materials joined with printing and transfer methods to effect their integration within functional modules. Here, we emphasize in this review considerations of the design strategies and assembly techniques that, when taken together, circumvent limitations imposed by approaches that integrate circuit elements within compact, rigid, and essentially planar form factor devices, and provide a transformational set of capabilities for high performance flexible/stretchable electronics.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Threshold Switching and Memory Behaviors of Epitaxially Regrown GaN-on-GaN Vertical $p-n$ Diodes With High Temperature Stability

This letter reports the observation of threshold switching and memory behaviors of epitaxially regrown GaN-on-GaN vertical p-n diodes. This mechanism was ascribed to the conductive path formed by traps in the insulating layer at the regrowth interface after soft breakdown. The device can reliably switch more than 1000 cycles at both room temperature and 300 °C with small fluctuation on the set and reset voltage. The set voltage increased with the increasing temperature due to the enhanced thermal detrapping effect that made it harder to form conductive path at high temperatures. Besides, the device showed memory behaviors when the reset voltage was higher than 4.4 V. This letter can serve as an important reference to further developing GaN-based memory devices and integrated circuits.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Throwing computing into reverse

For more than 50 years, computers have made steady and dramatic improvements, all thanks to Moore’s Law—the exponential increase over time in the number of transistors that can be fabricated on an integrated circuit of a given size. Moore’s Law owed its success to the fact that as transistors were made smaller, they became simultaneously cheaper, faster, and more energy efficient. The payoff from this win-win-win scenario enabled reinvestment in semiconductor fabrication technology that could make even smaller, more densely-packed transistors. And so this virtuous cycle continued, decade after decade. Now though, experts in industry, academia, and government laboratories anticipate that semiconductor miniaturization won’t continue much longer—maybe 10 years or so, at best. Making transistors smaller no longer yields the improvements it used to. The physical characteristics of small transistors forced clock speeds to cease getting faster more than a decade ago, which drove the industry to start building chips with multiple cores. But even multi-core architectures must contend with increasing amounts of “dark silicon,” areas of the chip that must be powered off to avoid overheating.

Energy efficiency↗
DOE OSTI2016

Optimizing Floating Guard Ring Designs for FASPAX N-in-P Silicon Sensors

FASPAX (Fermi-Argonne Semiconducting Pixel Array X-ray detector) is being developed as a fast integrating area detector with wide dynamic range for time resolved applications at the upgraded Advanced Photon Source (APS.) A burst mode detector with intended $\mbox{13 $MHz$}$ image rate, FASPAX will also incorporate a novel integration circuit to achieve wide dynamic range, from single photon sensitivity to $10^{\text{5}}$ x-rays/pixel/pulse. To achieve these ambitious goals, a novel silicon sensor design is required. This paper will detail early design of the FASPAX sensor. Results from TCAD optimization studies, and characterization of prototype sensors will be presented.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗