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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,369 records · Page 76
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

High Mobility SiGe/Si n-Type Structures and Field Effect Transistors on Sapphire Substrates

SiGe/Si n-type modulation doped field effect transistors (MODFETs) fabricated on sapphire substrates have been characterized at microwave frequencies for the first time. The highest measured room temperature electron mobility is 1380 sq cm/V-sec at a carrier density of 1.8 x 10(exp 12)/sq cm for a MODFET structure, and 900 sq cm/V-sec at a carrier density of 1.3 x 10/sq cm for a phosphorus ion implanted sample. A two finger, 2 x 200 micron gate n-MODFET has a peak transconductance of 37 mS/mm at a drain to source voltage of 2.5 V and a transducer gain of 6.4 dB at 1 GHz.

Alterovitz, Samuel A.↗
NASA NTRS2006

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Pinto, N. J.↗
NASA NTRS2002

The four-gate transistor

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

neuro-prosthetic devices cortical signals↗
NASA NTRS1993

16 Micrometer Infrared Hot Electron Transistor

We have demonstrated a bound to continuum state GaAs/Al_xGa_(1-x)As infrared hot electron transistor which has a peak response at theta_p = 16.3 micrometers. An excellent photo-current transfer ratio of alpha_p = 0.12 and very low dark current transfer ratio of alpha_d = 7.2x10^(-5) is achieved at a temperature of T = 60 K.

Gunapala, S. D.↗
NASA NTRS2006

Switching Characteristics of a 4H-SiC Based Bipolar Junction Transistor to 200 C

Static curves and resistive load switching characteristics of a 600 V, 4 A rated, SiC-based NPN bipolar power transistor (BJT) were observed at selected temperatures from room to 200 C. All testing was done in a pulse mode at low duty cycle (approx.0.1 percent). Turn-on was driven by an adjustable base current pulse and turn-off was accelerated by a negative base voltage pulse of 7 V. These base drive signals were implemented by 850 V, gated power pulsers, having rise-times of roughly 10 ns, or less. Base charge sweep-out with a 7 V negative pulse did not produce the large reverse base current pulse seen in a comparably rated Si-based BJT. This may be due to a very low charge storage time. The decay of the collector current was more linear than its exponential-like rise. Switching observations were done at base drive currents (I(sub B)) up to 400 mA and collector currents (I(sub C)) up to 4 A, using a 100 Omega non-inductive load. At I(sub B) = 400 mA and I(sub C) = 4 A, turn-on times typically varied from 80 to 94 ns, over temperatures from 23 to 200 C. As expected, lowering the base drive greatly extended the turn-on time. Similarly, decreasing the load current to I(sub C) = 1 A with I(sub B) = 400 mA produced turn-on times as short as 34 ns. Over the 23 to 200 C range, with I(sub B) = 400 mA and I(sub C) = 4 A, turn-off times were in the range of 72 to 84 ns with the 7 V sweep-out.

Niedra, Janis M.↗
NASA NTRS2006

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

Niedra, Janis M.↗
NASA NTRS2007

Fabrication of a Thermally Isolated and Pre-amplified Transistor Module with Polyimide Micro-wires for Cryogenic Detectors

For use in cryogenic applications such as bolometer and x-ray microcalorimeter arrays, pre-amplifying Junction Field Effect Transistors (JFETs) are often required for the readout electronics. The optimum operating temperature of the JFETs is 130 Kelvin while the cryogenic detectors operate in the milli-Kelvin range. Thus, the JFETs must be heated up but thermally isolated from the surrounding cryogenic instruments. In the past, the thermal isolation was accomplished by suspending the JFETs with low conductance wires such as manganium or stainless steel on a Kevlar support platform [I]. This also achieved electrical connections. However, this assembly required manual soldering work, which could raise a reliability issue for the cryogenic applications. In order to eliminate the manual work, polyimide micro-wires were developed [2]. The wires must be of sufficient length to decrease the heat load and in tension to prevent microphonic noise from vibration of the wires: the polyimide wires were patterned into llS"shaped curves over a thin metal wires such as aluminum, titanium, or niobium. The bilayer of the films were then suspended by etching silicon substrate thus to make freestanding air bridges (enough explanation?). In this paper, we present a method to fabricate micromachined JFET mechanical modules suspended by polyimide Pyraline micro-wires and heated up with built-in aluminum micro-heaters.

Oh, L. H.↗
NASA NTRS1983

Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques

A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

Policastro, Steven G.↗
NASA NTRS2007

Flexible carbon-based ohmic contacts for organic transistors

The present invention relates to a system and method of organic thin-film transistors (OTFTs). More specifically, the present invention relates to employing a flexible, conductive particle-polymer composite material for ohmic contacts (i.e. drain and source).

Brandon, Erik↗
NASA NTRS2004

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

global optimization↗
NASA NTRS2009

InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

Radisic, Vesna↗
NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗
NASA NTRS2009

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

MacLeod, Todd C.↗