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At least 127 records · Page 7

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NASA NTRS1989

Process for coating an object with silicon carbide

A process for coating a carbon or graphite object with silicon carbide by contacting it with silicon liquid and vapor over various lengths of contact time. In the process, a stream of silicon-containing precursor material in gaseous phase below the decomposition temperature of said gas and a co-reactant, carrier or diluent gas such as hydrogen is passed through a hole within a high emissivity, thin, insulating septum into a reaction chamber above the melting point of silicon. The thin septum has one face below the decomposition temperature of the gas and an opposite face exposed to the reaction chamber. The precursor gas is decomposed directly to silicon in the reaction chamber. A stream of any decomposition gas and any unreacted precursor gas from said reaction chamber is removed. The object within the reaction chamber is then contacted with silicon, and recovered after it has been coated with silicon carbide.

Levin, Harry↗

NASA NTRS1978

Advances in the Dow Corning process for solar-grade silicon

The Dow Corning process consists of the carbothermic reduction of silica to produce silicon that is then purified by unidirectional solidification. The process has produced silicon of semiconductor quality with respect to all elements except boron and phosphorus at about 10 ppma and aluminum at 0.1 ppma. Solar cells produced from this silicon gave AM0 conversion efficiencies of 11%. A process cost analysis is presented.

Hunt, L. P.↗

NASA NTRS1978

Silicon solar cell process development, fabrication and analysis

A program plan, baseline process, measurement program and quality control plan were generated. Cutting operations were completed on the silicon sheet material. The first fabrication run of polycrystalline silicon into solar cells by baseline process was completed. Average conversion efficiency for solar cells fabricated by the baseline process from sheet and measured at air mass zero was 10.4%, compared with the control cells, fabricated from single crystal CZ silicon, whose average conversion efficiency was 12.2%.

Source record↗

NASA NTRS1977

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

Source record↗

NASA NTRS1981

Silicon solar cell process development, fabrication and analysis

The fabrication of solar cells from several unconventional silicon materials is described, and cell performance measured and analyzed. Unconventional materials evaluated are edge defined film fed grown (EFG), heat exchanger method (HEM), dendritic web grown, and continuous CZ silicons. Resistivity, current voltage, and spectral sensitivity of the cells were measured. Current voltage was measured under AM0 and AM1 conditions. Maximum conversion efficiencies of cells fabricated from these and other unconventional silicons were compared and test results analyzed. The HEM and continuous CZ silicon were found to be superior to silicon materials considered previously.

Minahan, J. A.↗

NASA NTRS1979

The Establishment of a Production-ready Manufacturing Process Utilizing Thin Silicon Substrates for Solar Cells

During the months of February and March, work towards the goals of the contract were started as scheduled. The first shipment of thin substrates were received and wafer processing was initiated. The objective of the contract is to investigate, develop and characterize the methods for establishing a production-ready manufacturing process which utilizes thin silicon substrates for solar cells. The thin substrates to be manufactured are three inches diameter, p-type Czochralski wafers of approximately 1 Omega cm resistivity. The wafers are prepared by sawing directly to thickness of 8 mils and 5 mils. To ensure removal of residual saw damage, most substrates are chemically etched to final thicknesses of 7 mils and 4 mils. The thin substrates are used to fabricate solar cells by standard processing techniques.

Pryor, R. A.↗

NASA NTRS1979

Silicon Solar Cell Process Development, Fabrication and Analysis

The standard solar cells (2x2 cm) from the cast silicon (HEM) showed a maximum AMO efficiency of 10.1%. Cells from the low resistivity material (0.5 ohm-cm) showed lower performance than those of the high resistivity cast silicon (3 ohm-cm), an average efficiency 9.5% versus 7.6%. Maximum AMO efficiency of the standard solar cells from the EFG (RH) ribbons was about 7.5%. The solar cells from the controlled SiC, using the displaced die, showed more consistent and better performance than those of the uncontrolled SiC ribbons, an average efficiency of 6.6% versus 5.4%. The average AMO efficiency of the standard SOC solar cells were about 6%. These were large area solar cells (an average area of 15 sq cm). A maximum efficiency of 7.3% was obtained. The SOC solar cells showed both leakage and series resistance problems, leading to an average curve fill factor of about 60%.

Yoo, H. I.↗

NASA NTRS1979

Silicon Solar Cell Process Development, Fabrication and Analysis

The standard solar cells (2x2 cm) from the cast silicon heatexchanger method) showed a maximum AMO efficiency of 10.1%. Cells from low resistivity material (0.5 ohm-cm) showed lower performance than those of the high resistivity cast silicon (3 ohm-cm), an average efficiency 9.5% versus 7.6% Maximum AMO efficiency of the standard solar cells (2x2 cm) from the EFG (RH) ribbons was about 7.5%. The solar cells from controlled SiC, using the displaced die, showed more consistent and better performance than those of the uncontrolled SiC ribbons, an average efficiency of 6.6% versus 5.4% The average AMO efficiency of the standard silicon ceramic (soc) solar calls were about 6%. These were large area solar cells (an average area of 15 sq cm). A maximum efficiency of 7.3% was obtained. The SOC solar cells showed both leakage and series resistance problems, leading to an average curve fill factor of about 60%.

Yoo, H. I.↗

NASA NTRS1984

Process research of non-CZ silicon material

Advanced processing techniques for non-CZ silicon sheet material that might improve the cost effectiveness of photovoltaic module production were investigated. Specifically, the simultaneous diffusion of liquid boron and liquid phosphorus organometallic precursors into n-type dendritic silicon web was examined. The simultaneous junction formation method for solar cells was compared with the sequential junction formation method. The electrical resistivity of the n-n and p-n junctions was discussed. Further research activities for this program along with a program documentation schedule are given.

Campbell, R. B.↗

NASA NTRS1981

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Redfield, D.↗

NASA NTRS1979

Formation of porous surface layers in reaction bonded silicon nitride during processing

An effort was undertaken to determine if the formation of the generally observed layer of large porosity adjacent to the as-nitride surfaces of reaction bonded silicon nitrides could be prevented during processing. Isostatically pressed test bars were prepared from wet vibratory milled Si powder. Sintering and nitriding were each done under three different conditions:(1) bars directly exposed to the furnance atmosphere; (2) bars packed in Si powder; (3) bars packed in Si3N4 powder. Packing the bars in either Si of Si3N4 powder during sintering retarded formation of the layer of large porosity. Only packing the bars in Si prevented formation of the layer during nitridation. The strongest bars (316 MPa) were those sintered in Si and nitrided in Si3N4 despite their having a layer of large surface porosity; failure initiated at very large pores and inclusions. The alpha/beta ratio was found to be directly proportional to the oxygen content; a possible explanation for this relationship is discussed.

Shaw, N. J.↗

NASA NTRS1968

Improved process for epitaxial deposition of silicon on prediffused substrates

Process for fabricating integrated circuits uniformly deposits silicon epitaxially on prediffused substrates without affecting the sublayer diffusion pattern. Two silicon deposits from different sources, and deposited at different temperatures, protect the sublayer pattern from the silicon tetrachloride reaction.

Clarke, M. G.↗

NASA NTRS1978

Improved reaction sintered silicon nitride

Processing treatments were applied to as-nitrided reaction sintered silicon nitride (RSSN) with the purposes of improving strength after processing to above 350 MN/m2 and improving strength after oxidation exposure. The experimental approaches are divided into three broad classifications: sintering of surface-applied powders; impregnation of solution followed by further thermal processing; and infiltration of molten silicon and subsequent carburization or nitridation of the silicon. The impregnation of RSSN with solutions of aluminum nitrate and zirconyl chloride, followed by heating at 1400-1500 C in a nitrogen atmosphere containing silicon monoxide, improved RSSN strength and oxidation resistance. The room temperature bend strength of RSSN was increased nearly fifty percent above the untreated strength with mean absolute strengths up to 420 MN/m2. Strengths of treated samples that were measured after a 12 hour oxidation exposure in air were up to 90 percent of the original as-nitrided strength, as compared to retained strengths in the range of 35 to 60 percent for untreated RSSN after the same oxidation exposure.

Baumgartner, H. R.↗

NASA NTRS1980

The establishment of a production-ready manufacturing process utilizing thin silicon substrates for solar cells

Three inch diameter Czochralski silicon substrates sliced directly to 5 mil, 8 mil, and 27 mil thicknesses with wire saw techniques were procured. Processing sequences incorporating either diffusion or ion implantation technologies were employed to produce n+p or n+pp+ solar cell structures. These cells were evaluated for performance, ease of fabrication, and cost effectiveness. It was determined that the use of 7 mil or even 4 mil wafers would provide near term cost reductions for solar cell manufacturers.

Pryor, R. A.↗

NASA NTRS1981

Silicon solar cell process development, fabrication and analysis

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Yoo, H. I.↗

NASA NTRS1982

Process Research On Polycrystalline Silicon Material (PROPSM)

Performance limiting mechanisms in polycrystalline silicon are investigated by fabricating a matrix of solar cells of various thicknesses from polycrystalline silicon wafers of several bulk resistivities. The analysis of the results for the entire matrix indicates that bulk recombination is the dominant factor limiting the short circuit current in large grain (greater than 1 to 2 mm diameter) polycrystalline silicon, the same mechanism that limits the short circuit current in single crystal silicon. An experiment to investigate the limiting mechanisms of open circuit voltage and fill factor for large grain polycrystalline silicon is designed. Two process sequences to fabricate small cells are investigated.

Culik, J. S.↗

NASA NTRS1982

Process Research ON Semix Silicon Materials (PROSSM)

A cost effective process sequence was identified, equipment was designed to implement a 6.6 MW per year automated production line, and a cost analysis projected a $0.56 per watt cell add-on cost for this line. Four process steps were developed for this program: glass beads back clean-up, hot spray antireflective coating, wave soldering of fronts, and ion milling for edging. While spray dopants were advertised as an off the shelf developed product, they were unreliable with shorter than advertised shelf life.

Wohlgemuth, J. H.↗

NASA NTRS1981

Silicon solar cell process development, fabrication, and analysis

Work has progressed in fabrication and characterization of solar cells from ubiquitous crystallization process (UCP) wafers and LASS ribbons. Gettering tests applied to UCP wafers made little change on their performance compared with corresponding baseline data. Advanced processes such as shallow junction (SJ), back surface field (BSF), and multilayer antireflection (MLAR) were also applied. While BSF by Al paste had shunting problems, cells with SJ and BSF by evaporated Al, and MLAR did achieve 14.1% AMI on UCP silicon. The study of LASS material was very preliminary. Only a few cells with SJ, BSR, (no BSF) and MLAR were completed due to mechanical yield problems after lapping the material. Average efficiency was 10.7% AMI with 13.4% AMI for CZ controls. Relatively high minority carrier diffusion lengths were obtained. The lower than expected Jsc could be partially explained by low active area due to irregular sizes.

Yoo, H. I.↗