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At least 127 records · Page 7

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NASA NTRS1989

Fast Asynchronous Data Communication Via Fiber Optics

Transmitter and receiver devised for asynchronous digital communication via optical fiber at rates above 100 Mb/s. Transmitter converts parallel data to serial for high-speed transmission; receiver recovers clock signal and converts data back to parallel. No phase-lock loops used. New receiver design avoids over-sampling altogether. Local sampling oscillator operating nominally at clock frequency generates N clock signals of equally spaced phase, used to clock incoming data into N separate shift registers.

Bergman, Larry A.↗

NASA NTRS1989

Pass-transistor asynchronous sequential circuits

Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N + M times.

Whitaker, Sterling R.↗

NASA NTRS1989

Parallel asynchronous systems and image processing algorithms

A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.

Coon, D. D.↗

NASA NTRS1989

Asynchronous multilevel adaptive methods for solving partial differential equations on multiprocessors - Performance results

The fast adaptive composite grid method (FAC) is an algorithm that uses various levels of uniform grids (global and local) to provide adaptive resolution and fast solution of PDEs. Like all such methods, it offers parallelism by using possibly many disconnected patches per level, but is hindered by the need to handle these levels sequentially. The finest levels must therefore wait for processing to be essentially completed on all the coarser ones. A recently developed asynchronous version of FAC, called AFAC, completely eliminates this bottleneck to parallelism. This paper describes timing results for AFAC, coupled with a simple load balancing scheme, applied to the solution of elliptic PDEs on an Intel iPSC hypercube. These tests include performance of certain processes necessary in adaptive methods, including moving grids and changing refinement. A companion paper reports on numerical and analytical results for estimating convergence factors of AFAC applied to very large scale examples.

Mccormick, S.↗

NASA NTRS1991

Using process groups to implement failure detection in asynchronous environments

Agreement on the membership of a group of processes in a distributed system is a basic problem that arises in a wide range of applications. Such groups occur when a set of processes cooperate to perform some task, share memory, monitor one another, subdivide a computation, and so forth. The group membership problems is discussed as it relates to failure detection in asynchronous, distributed systems. A rigorous, formal specification for group membership is presented under this interpretation. A solution is then presented for this problem.

Ricciardi, Aleta M.↗

NASA NTRS1991

An advanced OBP-based payload operating in an asynchronous network for future data relay satellites utilising CCSDS-standard data structures

A possible Data Relay Satellite System (DRSS) topology and network architecture is introduced. An asynchronous network concept, whereby each link (Inter-orbit, Inter-satellite, Feeder) is allowed to operate on its own clock, without causing loss of information, in conjunction with packet data structures, such as those specified by the CCSDS for advanced orbiting systems is discussed. A matching OBP payload architecture is described, highlighting the advantages provided by the OBP-based concept and then giving some indications on the OBP mass/power requirements.

Grant, M.↗

NASA NTRS1972

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

Source record↗

NASA NTRS1993

Process membership in asynchronous environments

The development of reliable distributed software is simplified by the ability to assume a fail-stop failure model. The emulation of such a model in an asynchronous distributed environment is discussed. The solution proposed, called Strong-GMP, can be supported through a highly efficient protocol, and was implemented as part of a distributed systems software project at Cornell University. The precise definition of the problem, the protocol, correctness proofs, and an analysis of costs are addressed.

Ricciardi, Aleta M.↗

NASA NTRS1992

Self synchronized asynchronous sequential pass transfer circuits

A new class of CMOS VLSI asynchronous sequential circuits utilizing pass transistors is introduced. This class of self synchronizing circuits eliminates the need for critical race free state assignments. These circuits synchronize the transition path action by forcing the circuit to sequence through proper unstable states.

Whitaker, Sterling R.↗

NASA NTRS1993

Asynchronous transfer mode link performance over ground networks

The results of an experiment to determine the feasibility of using asynchronous transfer mode (ATM) technology to support advanced spacecraft missions that require high-rate ground communications and, in particular, full-motion video are reported. Potential nodes in such a ground network include Deep Space Network (DSN) antenna stations, the Jet Propulsion Laboratory, and a set of national and international end users. The experiment simulated a lunar microrover, lunar lander, the DSN ground communications system, and distributed science users. The users were equipped with video-capable workstations. A key feature was an optical fiber link between two high-performance workstations equipped with ATM interfaces. Video was also transmitted through JPL's institutional network to a user 8 km from the experiment. Variations in video depending on the networks and computers were observed, the results are reported.

Chow, E. T.↗

NASA NTRS1993

A formal language for the specification and verification of synchronous and asynchronous circuits

A formal hardware description language for the intended application of verifiable asynchronous communication is described. The language is developed within the logical framework of the Nqthm system of Boyer and Moore and is based on the event-driven behavioral model of VHDL, including the basic VHDL signal propagation mechanisms, the notion of simulation deltas, and the VHDL simulation cycle. A core subset of the language corresponds closely with a subset of VHDL and is adequate for the realistic gate-level modeling of both combinational and sequential circuits. Various extensions to this subset provide means for convenient expression of behavioral circuit specifications.

Russinoff, David M.↗

NASA NTRS1991

Asynchronous sequential circuit design using pass transistor iterative logic arrays

The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

Liu, M. N.↗

NASA NTRS1993

Faulty behavior of asynchronous storage elements

It is often assumed that the faults in storage elements (SE's) can be modeled as output/input stuck-at-faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. A more accurate higher level fault model for elementary SE's used in asynchronous circuits is presented. This model offers better representation of the physical failures. It is shown that the stuck-at model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SE's that are not covered by the stuck-at model. These include data-feed-through behaviors that cause the SE to be combinational. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit.

Al-Assadi, Waleed K.↗

NASA NTRS1994

DAI-CLIPS: Distributed, Asynchronous, Interacting CLIPS

DAI-CLIPS is a distributed computational environment within which each CLIPS is an active independent computational entity with the ability to communicate freely with other CLIPS. Furthermore, new CLIPS can be created, others can be deleted or modify their expertise, all dynamically in an asynchronous and independent fashion during execution. The participating CLIPS are distributed over a network of heterogeneous processors taking full advantage of the available processing power. We present the general framework encompassing DAI-CLIPS and discuss some of its advantages and potential applications.

Gagne, Denis↗

NASA NTRS1995

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Russinoff, David M.↗

NASA NTRS1995

The remarkable eclipsing asynchronous AM Herculis binary RX J19402-1025

We report on two years of photometric and spectroscopic observation of the recently discovered AM Herculis star RX J19402-1025. A sharp eclipse feature is present in the optical and X-ray light curves, repeating with a period of 12116.290 +/- 0.003 s. The out-of-eclipse optical waveform contains approximately equal contributions from a signal at the same period and another signal at 12150 s. As these signals drift in and out of phase, the wave form of the light curve changes in a complex but predictable manner. After one entire 'supercycle' of 50 days (the beat period between the shorter periods), the light curve returns to its initial shape. We present long-term ephemerides for each of these periods. It is highly probable that the eclipse period is the underlying orbital period, while the magnetic white dwarf rotates with P = 12150 s. The eclipses appear to be eclipses of the white dwarf by the secondary star. But there is probably also a small obscuring effect from cold gas surrounding the secondary, especially on the orbit-leading side where the stream begins to fall towards the white dwarf. The latter hypothesis can account for several puzzling effects in this star, as well as the tendency among most AM Her stars for the sharp emission-line components to slightly precede the actual motion of the secondary. The presence of eclipses in an asynchronous AM Her star provides a marvelous opportunity to study how changes in the orientation of magnetic field lines affect the accretion flows. Repeated polarimetric light curves and high-resolution studies of the emission lines are now critical to exploit this potential.

Patterson, Joseph↗

NASA NTRS1998

MPEG-2 Over Asynchronous Transfer Mode (ATM) Over Satellite Quality of Service (QoS) Experiments: Laboratory Tests

Asynchronous transfer mode (ATM) quality of service (QoS) experiments were performed using MPEG-2 (ATM application layer 5, AAL5) over ATM over an emulated satellite link. The purpose of these experiments was to determine the free-space link quality necessary to transmit high-quality multimedia information by using the ATM protocol. The detailed test plan and test configuration are described herein as are the test results. MPEG-2 transport streams were baselined in an errored environment, followed by a series of tests using, MPEG-2 over ATM. Errors were created both digitally as well as in an IF link by using a satellite modem and commercial gaussian noise test set for two different MPEG-2 decoder implementations. The results show that ITU-T Recommendation 1.356 Class 1, stringent ATM applications will require better link quality than currently specified; in particular, cell loss ratios of better than 1.0 x 10(exp -8) and cell error ratios of better than 1.0 x 10(exp -7) are needed. These tests were conducted at the NASA Lewis Research Center in support of satellite-ATM interoperability research.

Ivancic, William D.↗

NASA NTRS1995

Asynchronous Transfer Mode (ATM) Switch Technology and Vendor Survey

Asynchronous Transfer Mode (ATM) switch and software features are described and compared in order to make switch comparisons meaningful. An ATM switch's performance cannot be measured solely based on its claimed switching capacity; traffic management and congestion control are emerging as the determining factors in an ATM network's ultimate throughput. Non-switch ATM products and experiences with actual installations of ATM networks are described. A compilation of select vendor offerings as of October 1994 is provided in chart form.

Berry, Noemi↗