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Results for “MEMORY DEVICES”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2014

Low latency and persistent data storage

Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Low latency and persistent data storage

Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Antiferromagnetic memory storage devices from magnetic transition metal dichalcogenides

Switchable antiferromagnetic (AFM) memory devices are provided based on magnetically intercalated transition metal dichalcogenides (TMDs) of the form AxMC2, where A is a magnetic element of stoichiometry x between 0 and 1, M is a transition metal of stoichiometry 1, and C is a chalcogen of stoichiometry 2. Memory storage is achieved by fabricating these materials into crosses of two or more bars and driving DC current pulses along the bars to rotate the AFM order to a fixed angle with respect to the current pulse. Application of current pulses along different bars can switch the AFM order between multiple directions. Standard resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by the input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.

Analytis, James G.↗
DOE OSTI2016

Resistively heated shape memory polymer device

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

36 MATERIALS SCIENCE↗
DOE OSTI2017

Resistively heated shape memory polymer device

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

Marion, III, John E.↗
DOE OSTI2017

Resistively heated shape memory polymer device

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

Marion, III, John E.↗
DOE OSTI2011

All-optical active plasmonic devices with memory and power-switching functionalities based on {epsilon}-near-zero nonlinear metamaterials

We theoretically propose and numerically investigate an active plasmonic device made up of a nonlinear {epsilon}-near-zero metamaterial slab of thickness smaller than 100 nm lying on a linear {epsilon}-near-zero metamaterial substrate. We predict that in free-space coupling configuration the system operating at low intensity displays plasmon mediated hysteresis behavior. The phase difference between the reflected and the incident optical waves turns out to be multivalued and dependent on the history of the excitation process. Such an hysteresis behavior allows the proposed system to be regarded as a memory device whose state is accessible by measuring either the mentioned phase difference or the power, which is multivalued as well, carried by the nonlinear plasmon wave. Since multiple plasmon powers comprise both positive and negative values, the device also operates as a switch of the plasmon power direction at each jump along an hysteresis loop.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2013

Extended write combining using a write continuation hint flag

A computing apparatus for reducing the amount of processing in a network computing system which includes a network system device of a receiving node for receiving electronic messages comprising data. The electronic messages are transmitted from a sending node. The network system device determines when more data of a specific electronic message is being transmitted. A memory device stores the electronic message data and communicating with the network system device. A memory subsystem communicates with the memory device. The memory subsystem stores a portion of the electronic message when more data of the specific message will be received, and the buffer combines the portion with later received data and moves the data to the memory device for accessible storage.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2012

Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al{sub 2}O{sub 3} film as the tunnel and blocking oxides for nonvolatile memory applications

Remote plasma atomic layer deposited (RPALD) Al{sub 2}O{sub 3} films were investigated to apply as tunnel and blocking layers in the metal-oxide-semiconductor capacitor memory utilizing Au nanocrystals (NCs) for nonvolatile memory applications. The interface stability of an Al{sub 2}O{sub 3} film deposited by RPALD was studied to observe the effects of remote plasma on the interface. The interface formed during RPALD process has high oxidation states such as Si{sup +3} and Si{sup +4}, indicating that RPALD process can grow more stable interface which has a small amount of fixed oxide trap charge. The significant memory characteristics were also observed in this memory device through the electrical measurement. The memory device exhibited a relatively large memory window of 5.6 V under a 10/-10 V program/erase voltage and also showed the relatively fast programming/erasing speed and a competitive retention characteristic after 10{sup 4} s. These results indicate that Al{sub 2}O{sub 3} films deposited via RPALD can be applied as the tunnel and blocking oxides for next-generation flash memory devices.

36 MATERIALS SCIENCE↗
DOE OSTI2021

GaN-based threshold switching device and memory diode

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Fu, Kai↗
DOE OSTI2022

GaN-based threshold switching device and memory diode

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Fu, Kai↗
NASA NTRS2018

A Novel 3D DRAM Memory Cube Architecture for Space Applications

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.

Yang-Scharlotta, Jean↗
NASA NTRS2011

Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

MacLeond, Todd C.↗
NASA NTRS2000

Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

Wulf, William A.↗
NASA NTRS2009

Nanoscale content-addressable memory

A combined content addressable memory device and memory interface is provided. The combined device and interface includes one or more one molecular wire crossbar memories having spaced-apart key nanowires, spaced-apart value nanowires adjacent to the key nanowires, and configurable switches between the key nanowires and the value nanowires. The combination further includes a key microwire-nanowire grid (key MNG) electrically connected to the spaced-apart key nanowires, and a value microwire-nanowire grid (value MNG) electrically connected to the spaced-apart value nanowires. A key or value MNGs selects multiple nanowires for a given key or value.

Davis, Bryan↗
DOE OSTI2014

Electrically tunable near-field radiative heat transfer via ferroelectric materials

We explore ways to actively control near-field radiative heat transfer between two surfaces that relies on electrical tuning of phonon modes of ferroelectric materials. Ferroelectrics are widely used for tunable electrical devices, such as capacitors and memory devices; however, their tunable properties have not yet been examined for heat transfer applications. We show via simulations that radiative heat transfer between two ferroelectric materials can be enhanced by over two orders of magnitude over the blackbody limit in the near field, and can be tuned as much as 16.5% by modulating the coupling between surface phonon polariton modes at the two surfaces via varying external electric fields. We then discuss how to maximize the modulation contrast for tunable thermal devices using the studied mechanism.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Memory operation devices based on light-illumination ambipolar carbon-nanotube thin-film-transistors

We report the memory operation behavior of a light illumination ambipolar single-walled carbon nanotube thin film field-effect transistors devices. In addition to the high electronic-performance, such an on/off transistor-switching ratio of 10{sup 4} and an on-conductance of 18 μS, these memory devices have shown a high retention time of both hole and electron-trapping modes, reaching 2.8 × 10{sup 4} s at room temperature. The memory characteristics confirm that light illumination and electrical field can act as an independent programming/erasing operation method. This could be a fundamental step toward achieving high performance and stable operating nanoelectronic memory devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Method of efficiently identifying rollback requests

Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allow a memory device to efficiently mark memory extents involved in an enhanced memory operation. An extent is marked if a meta state associated with the extent indicates that the extent is included in the enhanced memory operation. The largest memory extents of the operation are maintained in the memory device as a list of unmarked extents. When a primitive memory operation is received, the memory address is compared to the unmarked extents in the list to the meta state for that memory line. If the address is covered by the list of extents, or that line's meta state is marked, then the memory operation is performed including the enhanced memory operation.

Brewer, Tony M.↗