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CMOS Charged Particle Spectrometer chips [1], designated CPS32, have been developed for an experiment on the STRV-2 spacecraft. These chips, which are a form of Active Pixel Sensor (APS), were designed for proton and electron energy spectrometry.
A first-generation CMOS Charged Particle Spectrometer chip [1] was designed at JPL for flight on the STRV-2 spacecraft. These devices will collect electron and proton spectra in low Earth orbit as part of an experiment to demonstrate Active Pixel Sensor (APS) technology in space. This paper presents the results of total dose testing on these chips and, where possible, attempts to extend the results to other Active Pixel Sensors.
This paper gives the status of theoretical and experimental efforts at JPL in the development of environmentally robust (radiation hard and radiation tolerant), ultra-low power, high performance CMOS active pixel sensor (APS) imagers for star tracker/imager applications.
Dark Current degradation and Dark Current Ran- dom Telegraph Signal after proton irradiation are studied in new scale silicon microvolumes by using a commercial CMOS Image Sensor. Results show that previously reported empirical models describing the Displacement Damage induced degradations are still valid despite the 10 to 100 times smaller depletion volume used. In addition, no evidence of significant Total Ionizing Dose effects is observed. Finally the reduction of the fraction of Random Telegraph Signal (RTS) pixels detected and of the fraction of multi-level RTS pixels is directly linked to the reduction in pixel volume.
Breaking time-reversal symmetry by introducing magnetic order, thereby opening a gap in the topological surface state bands, is essential for realizing useful topological properties such as the quantum anomalous Hall and axion insulator states. In this work, a novel topological antiferromagnetic (AFM) phase is created at the interface of a sputtered, c-axis-oriented, topological insulator/ferromagnet heterostructure—Bi 2 Te 3 /Ni 80 Fe 20 because of diffusion of Ni in Bi 2 Te 3 (Ni-Bi 2 Te 3 ). The AFM property of the Ni-Bi2Te3 interfacial layer is established by observation of spontaneous exchange bias in the magnetic hysteresis loop and compensated moments in the depth profile of the magnetization using polarized neutron reflectometry. Analysis of the structural and chemical properties of the Ni-Bi2Te3 layer is carried out using selected-area electron diffraction, electron energy loss spectroscopy, and X-ray photoelectron spectroscopy. These studies, in parallel with first-principles calculations, indicate a solid-state chemical reaction that leads to the formation of Ni=Te bonds and the presence of topological antiferromagnetic (AFM) compound NiBi 2 Te 4 in the Ni-Bi 2 Te 3 interface layer. The Neél temperature of the Ni-Bi 2 Te 3 layer is ≈ 63 K, which is higher than that of typical magnetic topological insulators (MTIs). The presented results provide a pathway toward industrial complementary metal-oxide-semiconductor (CMOS)-process-compatible sputtered-MTI heterostructures, leading to novel materials for topological quantum devices.
High spatial resolution of ultracold neutron (UCN) measurement is of growing interest to UCN experiments such as UCN spectrometers, UCN polarimeters, quantum physics of UCNs, and quantum gravity. Here we utilize physics informed deep learning to enhance the experimental position resolution and to demonstrate sub-micron spatial resolutions for UCN position measurements obtained using a room-temperature CMOS sensor, extending our previous work that demonstrated a position uncertainty of 1.5 microns. We explore the use of the open-source software Allpix Squared to generate experiment-like synthetic hit images with ground-truth position labels. We use physics-informed deep learning by training a fully connected neural network (FCNN) to learn a mapping from input hit images to output hit position. The automated analysis for sub-micron position resolution in UCN detection combined with the fast data rates of current and next generation UCN sources will enable improved precision for future UCN research and applications.
Optical phase modulators operating at visible wavelengths are essential components for photonic technologies such as those for quantum control, communications, and laser ranging. However, they remain challenging to implement in scalable, integrated platforms capable of handling high optical powers. Here we present a visible-light, gigahertz-frequency acousto-optic phase modulator, fabricated on a 200-mm wafer in a volume CMOS foundry, that supports greater than 500 mW of optical power at 730 nm. The device combines a piezoelectric transducer and a photonic waveguide within a single, wavelength-scale structure that confines both a propagating optical mode and an electrically excitable breathing-mode mechanical resonance. By tuning the device’s geometry to optimize the optomechanical interaction, we achieve modulation depths up to 4.85 rad with 80 mW of applied microwave power at 2.31 GHz in a 2-mm-long device. This corresponds to resonant modulation figures of merit of V π = 1.32V and V π ⋅ L = 0.26V cm. To our knowledge, this is the lowest V π ever demonstrated in any acousto-optic phase modulator and represents a 15-fold reduction in V π and a 100-fold reduction in required microwave power relative to state-of-the-art modulators with high visible-wavelength power handling commonly employed in quantum control systems.
Hardened gated x-ray detectors use photographic film as the data recording medium due to its low sensitivity to the high-yield neutron environments at the National Ignition Facility (NIF). The photographic film is digitized with a Photometric Data Systems (PDS) microdensitometer, which measures the film’s optical density. The PDS scanner is able to measure a dynamic range of 0–5 OD; however, raster scanning the film is time consuming and maintenance of the instrument is challenging due to legacy technology. Since film usage at NIF is expected to continue in the foreseeable future, a digitization platform that is faster and more maintainable would benefit the NIF’s current and future operations. Here, this work presents the characterization of the digital transitions (DT) atom, a CMOS camera-based digitization platform that records film data in a single image capture very quickly and has widely available user support. The preliminary results suggest that the DT atom is able to reconstruct exposures accurately enough to be a competitive alternative to the PDS Scanner.
Abstract We tested a new model of CMOS detector manufactured by the Gpixel Inc, for potential space astronomical application. In laboratory, we obtain some bias images under the typical application environment. In these bias images, clear random row noise pattern is observed. The row noise also contains some characteristic spatial frequencies. We quantitatively estimated the impact of this feature to photometric measurements, by making simulated images. We compared different bias noise types under strict parameter control. The result shows the row noise will significantly deteriorate the photometric accuracy. It effectively increases the readout noise by a factor of 2–10. However, if it is properly removed, the image quality and photometric accuracy will be significantly improved.
Here, the Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.
Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Finally, further development of the eFPGA technology and its application to collider detector readout is discussed.
Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.
Integrated photonics operating at visible-near-infrared (VNIR) wavelengths offer scalable platforms for advancing optical systems for addressing atomic clocks, sensors, and quantum computers. The complexity of free-space control optics causes limited addressability of atoms and ions, and this remains an impediment on scalability and cost. Networks of Mach-Zehnder interferometers can overcome challenges in addressing atoms by providing high-bandwidth electro-optic control of multiple output beams. Here, we demonstrate a VNIR Mach-Zehnder interferometer on lithium niobate on sapphire with a CMOS voltage-level compatible full-swing voltage of 4.2 V and an electro-optic bandwidth of 2.7 GHz occupying only 0.35 mm 2 . Our waveguides exhibit 1.6 dB/cm propagation loss and our microring resonators have intrinsic quality factors of 4.4 × 10 5 . This specialized platform for VNIR integrated photonics can open new avenues for addressing large arrays of qubits with high precision and negligible cross-talk.
We showcase a CMOS-fabricated silicon photonic integrated circuit employing a bidirectionally pumped microring and polarization splitter-rotators for high-fidelity polarization entanglement. Spanning the optical C+L-band, this source is ideal for wavelength-multiplexed entanglement distribution in multi-user networks.
We showcase a fully on-chip CMOS-fabricated silicon photonic integrated circuit employing a bidirectionally pumped microring and polarization splitter-rotators tailored for the generation of broadband (>9 THz), high-fidelity (90–98%) polarization-entangled photons. Spanning the optical C+L-band and producing over 116 frequency-bin pairs on a 38.4-GHz-spaced grid, this source is ideal for flex-grid wavelength-multiplexed entanglement distribution in multiuser networks.
The Ultra-Fast X-ray Imager (UXI) program is an ongoing effort at Sandia National Laboratories to create high speed, multi-frame, time-gated Read Out Integrated Circuits (ROICs), and a corresponding suite of photodetectors to image a wide variety of High Energy Density (HED) physics experiments on both Sandia’s Z-Machine and LLNL’s National Ignition Facility (NIF). Several cameras have been designed over the length of the program; one of the most recent is the Icarus, which is an improvement on past imagers (Furi and Hippogriff). A second sensor that can be connected is the Daedalus sensor. The Icarus is a 1024 × 512-pixel array with either 25 μm or 8 µm spatial resolution containing four frames of storage per pixel and has improved timing generation and distribution components while achieved 2 ns time gating. The Daedalus sensor is also a 1024 x 512-pixel array with 25 µm special resolution containing three frames of storage per pixel and has an increased set of features for a wider variety of applications from interlacing of rows in each frame to configurability of all shutters. See Section 14 for details regarding the Icarus implementation of the firmware and Section 15 for details regarding the Daedalus implementation. Due to the unique test environments UXI sensors are targeted for, full custom hardware was required to physically mount an Icarus or Daedalus sensor, manage its various functions, and read out pixel data for transfer to a host computer. Beyond experimental functionality, the hardware also needed to accommodate sensor characterization requirements. Lawrence Livermore National Laboratory’s ‘Version 4.0 Board’ was the result of these efforts. It mounts all the components required to fully utilize the Icarus and Daedalus sensors including analog to digital converters to convert pixel data and various system voltages to digital form for readout and analysis, DAC channels for remote configuration of critical bias voltages, static random-access memories to buffer pixel data, RS422 and Gigabit Ethernet communications for remote access, and an FPGA to tie these components together. This document describes the FPGA electrical interfaces in detail to allow the reader a greater understanding of the device, and to facilitate implementation of custom software to control and manage it. The Version 4.0 Board is a continuation of the Nano-second Gated CMOS hardware design that retains much of the functionality of the Version 1.0 Board while adding features including a DAC instead of digital potentiometers, as well as sensors for pressure and radiation. The Version 4.0 board is intended for applications requiring tight form-factor enclosures. It is composed of two stacking boards; one holds the FPGA and regulators to power the various components of the board while the other contains the mating connector to the sensor, image-readoff ADCs, the DAC, and other components.
Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.
The goal of this CRADA was to understand high linearity silicon-on-insulator (SOI) radio frequency switches. The first direction investigated was high linearity RF mixers as these components are composed of a network of switches. During the course of the investigation, it was determined that while the SOI RF switches were effective in the application in mixers and produced state of the art performance, the use of SOI for mixers is not economically feasible because the technology only worked with advanced CMOS nodes <65nm which can have an NRE cost (from lithography masks) in excess of $\$$500,000.