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NASA NTRS1982

Part 2: Multi-wire slicing. Fixed Abrasive Slicing Technique (FAST)

The Fixed Abrasive Slicing Techniques (FAST) is a new slicing technique that was developed to slice ingots more effectively. It was demonstrated that 25 wafers/cm can be sliced from 10cm diameter and 19 wafers/cm from 15 cm diameter ingots. Over 99% yield (222 out of a possible 224) was demonstrated during slicing of a 10 cm diameter ingots at 25 wafers/cm. The average thickness of wafers was 0.249 mm and the kerf was 0.151 mm. Slicing rates as high as 0.14 mm/min were also demonstrated for 10 cm diameter ingots.

Source record↗
NASA NTRS1982

Silicon slicing by fixed abrasive slicing technique

One of the major cost factors in silicon ingot technology adaptation for terrestrial photovoltaic application is in slicing boules into wafers. The most developed industrial practice is the Internal Diameter (ID) slicing. This method utilizes diamond cutting. The diamond stands up for long periods, hence, the cost of expendable materials is low. However, the ID technology as practiced today has poor material utilization. The Multiblade Slurry (MBS) method has low equipment and labor costs but its expendable material costs are high. Recently Multiwire Slurry (MWS) technology has shown very good material utilization, but its expendable material costs are even higher than MBS. The multiwire Fixed Abrasive Slicing Technique (FAST) still in advanced development stage, combines the low expendable material costs of ID method, the low labor and equipment costs of MBS and high material utilization of MWS.

Schmid, F.↗
NASA NTRS1982

Test chips for custom ICs - Six kinds of test structures

Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.

Buehler, M. G.↗
NASA NTRS1982

Polycrystalline silicon availability for photovoltaic and semiconductor industries

Markets, applications, and production techniques for Siemens process-produced polycrystalline silicon are surveyed. It is noted that as of 1982 a total of six Si materials suppliers were servicing a worldwide total of over 1000 manufacturers of Si-based devices. Besides solar cells, the Si wafers are employed for thyristors, rectifiers, bipolar power transistors, and discrete components for control systems. An estimated 3890 metric tons of semiconductor-grade polycrystalline Si will be used in 1982, and 6200 metric tons by 1985. Although the amount is expected to nearly triple between 1982-89, research is being carried out on the formation of thin films and ribbons for solar cells, thereby eliminating the waste produced in slicing Czolchralski-grown crystals. The free-world Si production in 1982 is estimated to be 3050 metric tons. Various new technologies for the formation of polycrystalline Si at lower costs and with less waste are considered. New entries into the industrial Si formation field are projected to produce a 2000 metric ton excess by 1988.

Ferber, R. R.↗
NASA NTRS1982

Critical technology limits to silicon material and sheet production

Earlier studies have indicated that expenditures related to the preparation of high-purity silicon and its conversion to silicon sheet represent from 40 to 52 percent of the cost of the entire panel. The present investigation is concerned with the elements which were selected for study in connection with the Flat-Plate Solar Array (FSA) Project. The first of two technologies which are being developed within the FSA Project involves the conversion of metallurgical-grade silicon through a silane purification process to silicon particles. The second is concerned with the conversion of trichlorosilane to dichlorosilane, and the subsequent production of silicon using modified rod reactors of the Siemens type. With respect to silicon sheet preparation, efforts have been focused both on the preparation of ingots, followed by wafering, and the direct crystallization of molten silicon into a ribbon or film.

Leipold, M. H.↗
NASA NTRS1983

High-performance K-band GaAs power field-effect transistors prepared by molecular beam epitaxy

The maturity of the molecular beam epitaxy (MBE) technique for preparing device quality GaAs material for microwave applications is demonstrated by the excellent performance characteristics of K-band GaAs power field-effect transistors (FETs) fabricated on the MBE wafers. An output power of 710 mW with 4.5-dB gain and 17.7 percent power-added efficiency was achieved at 21 GHz with a 1.26-mm gate width pi-gate device. A similar device with a 0.56-mm gate width produced an output power of 320 mW with 5.0-dB gain and 26.6 percent power-added efficiency at 21 GHz. These are the best results yet reported to date for GaAs power FETs operated in the K-band frequency range.

Saunier, P.↗
NASA NTRS1985

Production Line for Dendritic-Web Solar Cells

Direct inclusion of web-growth furnaces in production line expected to result in lower costs than current production processes using silicon wafers sliced from Czochralski boules. Silicon-web input capacity of line is 0.5 m2/min, which corresponds to total peak-power output of about 25 MW for 1 year of production. Line employs about 18 production people per shift and requires about 3,650 square feet of floorspace.

Page, D. J.↗
NASA NTRS1983

Double-injection, deep-impurity switch development

The overall objective of this program is the development of device design and process techniques for the fabrication of a double-injection, deep-impurity (DI)(2) silicon switch that operates in the 1-10 kV range with conduction current of 10 and 1A, respectively. Other major specifications include a holding voltage of 0 to 5 volts at 1 A anode current, 10 microsecond switching time, and power dissipation of 50 W at 75 C. This report describes work that shows how the results obtained at the University of Cincinnati under NASA Grant NSG-3022 have been applied to larger area and higher voltage devices. The investigations include theoretical, analytical, and experimental studies of device design and processing. Methods to introduce deep levels, such as Au diffusion and electron irradiation, have been carried out to "pin down' the Fermi level and control device-switching characteristics. Different anode, cathode, and gate configurations are presented. Techniques to control the surface electric field of planar structures used for (DI)(2) switches are examined. Various sections of this report describe the device design, wafer-processing techniques, and various measurements which include ac and dc characteristics, 4-point probe, and spreading resistance.

Selim, F. A.↗
NASA NTRS1984

Deep diode arrays for X-ray detection

Temperature gradient zone melting process was used to form p-n junctions in bulk of high purity silicon wafers. These diodes were patterned to form arrays for X-ray spectrometers. The whole fabrication processes for these X-ray detectors are reviewed in detail. The p-n junctions were evaluated by (1) the dark diode I-V measurements, (2) the diode C sub I - V measurements, and (3) the MOS C-V measurements. The results showed that these junctions were linearly graded in charge distribution with low reverse bias leakage current flowing through them (few nA at -10 volts). The X-ray detection experiments showed that an FWHM of 500 eV was obtained from these diodes with a small bias of just -5 volts (for X-ray source Fe55). A theoretical model was proposed to explain the extra peaks found in the energy spectra and a very interesting point - cross talk effect was pointed out. This might be a solution to the problem of making really high resolution X-ray spectrometers.

Zemel, J. N.↗
NASA NTRS1983

Process Research On Polycrystalline Silicon Material (PROPSM)

The performance-limiting mechanisms in large-grain (greater than 1 to 2 mm in diameter) polycrystalline silicon solar cells were investigated by fabricating a matrix of 4 sq cm solar cells of various thickness from 10 cm x 10 cm polycrystalline silicon wafers of several bulk resistivities. Analysis of the illuminated I-V characteristics of these cells suggests that bulk recombination is the dominant factor limiting the short-circuit current. The average open-circuit voltage of the polycrystalline solar cells is 30 to 70 mV lower than that of co-processed single-crystal cells; the fill-factor is comparable. Both open-circuit voltage and fill-factor of the polycrystalline cells have substantial scatter that is not related to either thickness or resistivity. This implies that these characteristics are sensitive to an additional mechanism that is probably spatial in nature. A damage-gettering heat-treatment improved the minority-carrier diffusion length in low lifetime polycrystalline silicon, however, extended high temperature heat-treatment degraded the lifetime.

Culik, J. S.↗
NASA NTRS1982

Process Research On Polycrystalline Silicon Material (PROPSM)

Performance limiting mechanisms in polycrystalline silicon are investigated by fabricating a matrix of solar cells of various thicknesses from polycrystalline silicon wafers of several bulk resistivities. The analysis of the results for the entire matrix indicates that bulk recombination is the dominant factor limiting the short circuit current in large grain (greater than 1 to 2 mm diameter) polycrystalline silicon, the same mechanism that limits the short circuit current in single crystal silicon. An experiment to investigate the limiting mechanisms of open circuit voltage and fill factor for large grain polycrystalline silicon is designed. Two process sequences to fabricate small cells are investigated.

Culik, J. S.↗
NASA NTRS1984

Polycrystalline Silicon Sheets for Solar Cells by the Improved Spinning Method

Cost reduction of silicon materials in the photovoltaic program of materials was examined. The current process of producing silicon sheets is based entirely on the conventional Czochralski ingot growth and wafering used in the semiconductor industry. The current technology cannot meet the cost reduction demands for producing low cost silicon sheets. Alternative sheet production processes such as unconventional crystallization are needed. The production of polycrystalline silicon sheets by unconventional ingot technology is the casting technique. Though large grain sheets were obtained by this technique, silicon ribbon growth overcomes deficiencies of the casting process by obtaining the sheet directly from the melt. The need to solve difficulties of growth stability and impurity effects are examined. The direct formation process of polycrystalline silicon sheets with large grain size, smooth surface, and sharp edges from the melt with a high growth rate which will yield low cost silicon sheets for solar cells and the photovoltaic characteristics associated with this type of sheet to include an EBIC study of the grain boundaries are described.

Maeda, Y.↗
NASA NTRS1984

Electrical and Structural Characterization of Web Dendrite Crystals

Minority carrier lifetime distributions in silicon web dendrites are measured. Emphasis is placed on measuring areal homogeneity of lifetime, show its dependancy on structural defects, and its unique change during hot processing. The internal gettering action of defect layers present in web crystals and their relation to minority carrier lifetime distributions is discussed. Minority carrier lifetime maps of web dendrites obtained before and after high temperature heat treatment are compared to similar maps obtained from 100 mm diameter Czochralski silicon wafers. Such maps indicate similar or superior areal homogeneity of minority carrier lifetime in webs.

Schwuttke, G. H.↗
NASA NTRS1982

High density circuit technology, part 1

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

Wade, T. E.↗
NASA NTRS1984

Process in manufacturing high efficiency AlGaAs/GaAs solar cells by MO-CVD

Manufacturing technology for mass producing high efficiency GaAs solar cells is discussed. A progress using a high throughput MO-CVD reactor to produce high efficiency GaAs solar cells is discussed. Thickness and doping concentration uniformity of metal oxide chemical vapor deposition (MO-CVD) GaAs and AlGaAs layer growth are discussed. In addition, new tooling designs are given which increase the throughput of solar cell processing. To date, 2cm x 2cm AlGaAs/GaAs solar cells with efficiency up to 16.5% were produced. In order to meet throughput goals for mass producing GaAs solar cells, a large MO-CVD system (Cambridge Instrument Model MR-200) with a susceptor which was initially capable of processing 20 wafers (up to 75 mm diameter) during a single growth run was installed. In the MR-200, the sequencing of the gases and the heating power are controlled by a microprocessor-based programmable control console. Hence, operator errors can be reduced, leading to a more reproducible production sequence.

Yeh, Y. C. M.↗
NASA NTRS1983

Development of metallization process: FSA project, cell and module formation research area

This experiment is involved in determining bulk resistivity values for different past concentrations. Experiments were performed on silicon Cz and non-Cz wafers. To determine bulk resistivity more accurately, pastes were printed on ceramic substrates. Contact resistance was determined by measuring the voltage drop at constant current. Because of irregularity of grid profiles, accurate determination of cross sections of grid lines is difficult. The bulk resistivity is accurate when the resistivity of the metallization is much less than that of the layer beneath it. When the resistivity of the metal approaches that of the substrate, the actual resistivity will be larger than the measured value.

Garcia, A., III↗
NASA NTRS1984

Surface property modification of silicon

The main emphasis of this work has been to determine the wear rate of silicon in fluid environments and the parameters that influence wear. Three tests were carried out on single crystal Czochralski silicon wafers: circular and linear multiple-scratch tests in fluids by a pyramidal diamond simulated fixed-particle abrasion; microhardness and three-point bend tests were used to determine the hardness and fracture toughness of abraded silicon and the extent of damage induced by abrasion. The wear rate of (100) and (111) n and p-type single crystal Cz silicon abraded by a pyramidal diamond in ethanol, methanol, acetone and de-ionized water was determined by measuring the cross-sectional areas of grooves of the circular and linear multiple-scratch tests. The wear rate depends on the loads on the diamond and is highest for ethanol and lowest for de-ionized water. The surface morphology of the grooves showed lateral and median cracks as well as a plastically deformed region. The hardness and fracture toughness are critical parameters that influence the wear rate. Microhardness tests were conducted to determine the hardness as influenced by fluids. Median cracks and the damage zone surrounding the indentations were also related to the fluid properties.

Danyluk, S.↗
NASA NTRS1982

Directional solidification of silicon in carbon crucibles by an oscillating crucible technique

The quality of silicon cast by present techniques is limited by the presence of dislocations and grain boundaries in unseeded growth and by cellular structures with dislocation networks in the case of the seeded growth. To address these concerns, a new method of directional solidification called the oscillating crucible technique (OCT) is developed. During growth, a carbon crucible is oscillated to provide for effective stirring of the melt. This growth technique (seeded growth only), along with material characterization and solar-cell fabrication and testing, is described. Solar-cell efficiencies of up to 13 percent at 100 mW/sq cm area obtained in the single crystalline areas. Minority-carrier diffusion lengths exceeding 100 microns are measured even in the polycrystalline areas of the wafers. Limitations of the present setup and possible future improvements are discussed.

Daud, T.↗