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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Analysis and design of a second-order digital phase-locked loop

A specific second-order digital phase-locked loop (DPLL) was modeled as a first-order Markov chain with alternatives. From the matrix of transition probabilities of the Markov chain, the steady-state phase error of the DPLL was determined. In a similar manner the loop's response was calculated for a fading input. Additionally, a hardware DPLL was constructed and tested to provide a comparison to the results obtained from the Markov chain model. In all cases tested, good agreement was found between the theoretical predictions and the experimental data.

Blasche, P. R.↗
NASA NTRS1987

Predicting False Lock in Phase-Locked Loops

Theoretical paper discusses advances in mathematical analysis of phase-locked loops. Presents new results in prediction of false locking. Interest to users of phase-lock circuits and to researchers seeking ways to detect or avoid false lock. Equations solved numerically by Newton-Raphson technique, with Jacobian computed by finite-difference scheme. Algorithm produces results limited only by precision of computer on which executed.

Reed, Bill↗
NASA NTRS1974

Binary phase lock loops for simplified OMEGA receivers

A sampled binary phase lock loop is proposed for periodically correcting OMEGA receiver internal clocks. The circuit is particularly simple to implement and provides a means of generating long range 3.4 KHz difference frequency lanes from simultaneous pair measurements.

Burhans, R. W.↗
NASA NTRS1993

Method of implementing digital phase-locked loops

In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, or root-specific damping. Loops of first to fourth order are treated in the continuous-update approximation (BLT yields 0) and in a discrete-update formulation with arbitrary BLT. Deficiencies of the continuous-update approximation in large-BLT applications are avoided in the new discrete-update formulation. A new method for direct, transient-free acquisition with third- and fourth-order loops can improve the versatility and reliability of acquisition with such loops.

Stephens, Scott A.↗
NASA NTRS1997

Method of Implementing Digital Phase-Locked Loops

In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, and root-specific damping. Loops of first to fourth order are treated in the continuous-update approximation (B(sub L)T approaches 0) and in a discrete-update formulation with arbitrary B(sub L)T. Deficiencies of the continuous-update approximation in large-B(sub L)T applications are avoided in the new discrete-update formulation.

Stephens, Scott A.↗
NASA NTRS1974

On first cycle slip time of phase-locked loops in cascade

Precise measurement and spacecraft tracking are obtained by using phase-locked loops in cascade in two-way communications links. Statistics on cycle slip time are of vital importance in system planning and design. This paper presents: (1) results of a computer simulation study of the mean time to first cycle slip of cascade phase-locked loops preceded by bandpass limiters, and (2) the determination of probability distributions of cycle slip. Numerical results are obtained for a typical coherent communication system.

Yuen, J. H.↗
NASA NTRS1966

Electronic phase-locked-loop speed control system is stable

Phase locked-loop circuit is used for playback motors in digital tape recorders where the reproducer output remains in exact synchronism with an external reference clock over extended periods. It removes the motor dynamics from the control loop so that the loop is stable without damping.

Stone, F. A.↗
NASA NTRS1989

Ultrasonic pulsed phase locked loop interferometer for bolt load measurements

The pulsed phase-locked-loop bolt monitor (P2L2) that uses ultrasonic waves to measure bolt preload with accuracies ranging from 1 to 3 percent (depending on the specific bolt) is described. To remeasure bolt load after installation, a thermal calibration factor compensates for bolt temperature changes, and a standard reference block allows correction for acoustic phase errors due to measurement equipment configuration such as utilization of a different transducer, couplant, or cable. Some examples of critical applications including Space Shuttle landing-gear wheels and NASA wind-tunnel fan blades are discussed.

Allison, S. G.↗
NASA NTRS1973

An all digital phase locked loop for synchronization of a sinusoidal signal embedded in white Gaussian noise

An all digital phase locked loop which tracks the phase of the incoming sinusoidal signal once per carrier cycle is proposed. The different elements and their functions and the phase lock operation are explained in detail. The nonlinear difference equations which govern the operation of the digital loop when the incoming signal is embedded in white Gaussian noise are derived, and a suitable model is specified. The performance of the digital loop is considered for the synchronization of a sinusoidal signal. For this, the noise term is suitably modelled which allows specification of the output probabilities for the two level quantizer in the loop at any given phase error. The loop filter considered increases the probability of proper phase correction. The phase error states in modulo two-pi forms a finite state Markov chain which enables the calculation of steady state probabilities, RMS phase error, transient response and mean time for cycle skipping.

Reddy, C. P.↗
NASA NTRS1974

On the performance of digital phase locked loops in the threshold region

Extended Kalman filter algorithms are used to obtain a digital phase lock loop structure for demodulation of angle modulated signals. It is shown that the error variance equations obtained directly from this structure enable one to predict threshold if one retains higher frequency terms. This is in sharp contrast to the similar analysis of the analog phase lock loop, where the higher frequency terms are filtered out because of the low pass filter in the loop. Results are compared to actual simulation results and threshold region results obtained previously.

Hurst, G. T.↗
NASA NTRS1989

An analysis of digital phase-locked loops

This report focuses on second-order digital phase-locked loops (DPLLs) with uniformly sampled input, an amplitude-insenstive phase extractor and a conventional loop filter.

Thomas, J. B.↗
NASA NTRS1977

Analysis of a first order phase locked loop in the presence of Gaussian noise

A first-order digital phase locked loop is analyzed by application of a Markov chain model. Steady state loop error probabilities, phase standard deviation, and mean loop transient times are determined for various input signal to noise ratios. Results for direct loop simulation are presented for comparison.

Blasche, P. R.↗